MC68HC908MR8 Datasheet, PDF (308/372 Pages) Motorola, Inc – Microcontrollers

Low-Voltage Inhibit (LVI)
17.4.4 LVI Trip Selection
The TRPSEL bit allows the user to choose between 5 percent and
10 percent tolerance when monitoring the supply voltage. The
10 percent option is enabled out of reset. Writing a logic 1 to TRPSEL
will enable the 5 percent option.
NOTE: The MCU is guaranteed to operate at a minimum supply voltage. The trip
point (V_LVR1 or V_LVR2) may be lower than this.
17.5 LVI Status and Control Register
The LVI status register flags V_DD voltages below the V_LVRX level.
Ad-
dress:
$FE0F
Bit 7
6
5
4
3
2
1
Bit 0
Read: LVIOUT 0
TRPS-
0
0
0
0
0
Write: R
R
EL
R
R
R
R
R
Reset: 0
0
0
0
0
0
0
0
R = Reserved
Figure 17-3. LVI Status and Control Register (LVISCR)
LVIOUT — LVI Output Bit
This read-only flag becomes set when the V_DD voltage falls below the
V_LVRX voltage for 32 to 40 CGMXCLK cycles. See Table 17-1. Reset
clears the LVIOUT bit.
At level:
V_DD > V_LVRX + V_LVHX
V_DD < V_LVRX
V_DD < V_LVRX
V_DD < V_LVRX
Table 17-1. LVIOUT Bit Indication
V_DD
For number of CGMXCLK cycles:
Any
< 32 CGMXCLK CYCLES
Between 32 and 40 CGMXCLK cycles
> 40 CGMXCLK cycles
LVIOUT
0
0
0 or 1
1
Technical Data
308
Low-Voltage Inhibit (LVI)
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor