XC3S100E Datasheet, PDF (94/193 Pages) Xilinx, Inc – DC and Switching Characteristics

R
Functional Description
+1.2V
+1.2V
P
JTAG
Mode
‘1’
‘0’
‘1’
VCCINT
HSWAP
VCCO_0
VCCO_2
M2 _Spartan-3E
M1
FPGA
M0
TDI
TMS
TCK
VCCAUX
TDO
VCCO_0
VCCO_2
+2.5V
P
JTAG
Mode
‘1’
‘0’
‘1’
VCCINT
HSWAP
VCCO_0
VCCO_2
M2 _Spartan-3E
M1
FPGA
M0
TDI
TMS
TCK
VCCAUX
TDO
VCCO_0
VCCO_2
+2.5V
+2.5V
JTAG
TDI
TMS
TCK
TDO
PROG_B
DONE
GND
PROG_B
GND
DONE
Figure 62: JTAG Configuration Mode
TMS
TCK
DS312-2_56_021405
Voltage Compatibility
The 2.5V VCCAUX supply powers the JTAG interface. All of
the user I/Os are separately powered by their respective
VCCO_# supplies.
When connecting the Spartan-3E JTAG port to a 3.3V inter-
face, the JTAG input pins must be current-limited to 10 mA
or less using series resistors. Similarly, the TDO pin is a
CMOS output powered from +2.5V. The TDO output can
directly drive a 3.3V input but with reduced noise immunity.
See application note XAPP453: "The 3.3V Configuration of
Spartan-3 FPGAs" for additional information.
Maximum Bitstream Size for Daisy-Chains
The maximum bitstream length supported by Spartan-3E
FPGAs in serial daisy-chains is 4,294,967,264 bits (4
Gbits), roughly equivalent to a daisy-chain with 720
XC3S1600E FPGAs. This is a limit only for serial
daisy-chains where configuration data is passed via the
FPGA’s DOUT pin. There is no such limit for JTAG chains.
Configuration Sequence
The Spartan-3E configuration process is three-stage pro-
cess that begins after the FPGA powers on (a POR event)
or after the PROG_B input is asserted. Power-On Reset
(POR) occurs after the V_CCINT, VCCAUX, and the V_CCO Bank
2 supplies reach their respective input threshold levels.
After either a POR or PROG_B event, the three-stage con-
figuration process begins.
1. The FPGA clears (initializes) the internal configuration
memory.
2. Configuration data is loaded into the internal memory.
3. The user-application is activated by a start-up process.
Figure 63 is a generalized block diagram of the Spartan-3E
configuration logic, showing the interaction of different
device inputs and Bitstream Generator (BitGen) options. A
flow diagram for the configuration sequence of the Serial
and Parallel modes appears in Figure 64. Figure 65 shows
the Boundary-Scan or JTAG configuration sequence.
Initialization
Configuration automatically begins after power-on or after
asserting the FPGA PROG_B pin, unless delayed using the
FPGA’s INIT_B pin. The FPGA holds the open-drain INIT_B
signal Low while it clears its internal configuration memory.
Externally holding the INIT_B pin Low forces the configura-
tion sequencer to wait until INIT_B again goes High.
DS312-2 (v1.1) March 21, 2005
www.xilinx.com
87
Advance Product Specification