XC3S100E Datasheet, PDF (36/193 Pages) Xilinx, Inc – DC and Switching Characteristics

R
Functional Description
Parity
Data
Address
35 34 33 32 31
512x36 P3 P2 P1 P0
Byte 3
24 23
Byte 2
16 15
Byte 1
87
Byte 0
0
0
1Kx18
2K(1b^P6ia_tKs^rbi_p^t_i^y_tasr^O_idty^p_a)^t_taio_{, nal}
17 16 15
P3 P2
P1 P0
Byte 3
Byte 1
87
Byte 2
Byte 0
2Kx9
87
P3
P2
P1
P0
Byte 3
Byte 2
Byte 1
Byte 0
0
1
0
0
3
2
1
0
4Kx4
3 2 10
765
3^B2^{y te}1
3⁴
0
7
6
765
3^B2^yt1^e
0⁴
0
1
0
8Kx2
10
76 F
54 E
32 D
10 C
76 3
54 2
32 1
10 0
0
7 1F
6 1E
5 1D
4 1C
16Kx1
3₃
2₂
1₁
0₀
DS312-2_02_020705
Figure 28: Data Organization and Bus-matching Operation with Different Port Widths on Port A and Port B
Block RAM Port Signal Definitions
Representations of the dual-port primitive
RAMB16_S[w_A]_S[w_B] and the single-port primitive
RAMB16_S[w] with their associated signals are shown in
Figure 29a and Figure 29b, respectively. These signals are
defined in Table 20. The control signals (WE, EN, CLK, and
SSR) on the block RAM are active High. However, optional
inverters on the control signals change the polarity of the
active edge to active Low.
DS312-2 (v1.1) March 21, 2005
www.xilinx.com
29
Advance Product Specification