XC3S100E Datasheet, PDF (169/193 Pages) Xilinx, Inc – DC and Switching Characteristics

Pinout Descriptions
R
Table 24: FG320 Package Pinout (Continued)
Bank
3
3
3
3
3
3
3
3
XC3S500E Pin Name
IP
IP
IP
IP
IP
IP
IP/VREF_3
IO/VREF_3
XC3S1200E Pin Name
IP
IP
IP
IP
IP
IP
IP/VREF_3
IP/VREF_3
XC3S1600E Pin Name
IP
IP
IP
IP
IP
IP
IP/VREF_3
IP/VREF_3
3
3
3
3
3
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCCO_3
VCCO_3
VCCO_3
VCCO_3
VCCO_3
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
FG320
Ball
Type
K7
INPUT
M1
INPUT
N1
INPUT
N2
INPUT
R1
INPUT
U1
INPUT
J6
VREF
R4 500E: VREF(I/O)
1200E:
VREF(INPUT)
1600E:
VREF(INPUT)
F3
VCCO
H7
VCCO
K1
VCCO
L7
VCCO
N3
VCCO
A1
GND
A18
GND
B2
GND
B17
GND
C10
GND
G7
GND
G12
GND
H8
GND
H9
GND
H10
GND
H11
GND
J3
GND
J8
GND
J11
GND
K8
GND
K11
GND
K16
GND
L8
GND
L9
GND
48
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DS312-4 (v1.1) March 21, 2005
Advance Product Specification