XC3S100E Datasheet, PDF (138/193 Pages) Xilinx, Inc – DC and Switching Characteristics

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Table 12: TQ144 Package Pinout (Continued)
Bank
XC3S100E Pin Name
XC3S250E Pin Name
3
IO_L05N_3/LHCLK3/IRDY2
IO_L05N_3/LHCLK3
3
IO_L05P_3/LHCLK2
IO_L05P_3/LHCLK2
3
IO_L06N_3/LHCLK5
IO_L06N_3/LHCLK5
3
IO_L06P_3/LHCLK4/TRDY2
IO_L06P_3/LHCLK4
3
IO_L07N_3/LHCLK7
IO_L07N_3/LHCLK7
3
IO_L07P_3/LHCLK6
IO_L07P_3/LHCLK6
3
IO_L08N_3
IO_L08N_3
3
IO_L08P_3
IO_L08P_3
3
IO_L09N_3
IO_L09N_3
3
IO_L09P_3
IO_L09P_3
3
IO_L10N_3
IO_L10N_3
3
IO_L10P_3
IO_L10P_3
3
IP
IP
3
IO
IP
3
IP
IP
3
IP
IP
3
IO
IP
3
3
3
3
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
IP
IP/VREF_3
VCCO_3
VCCO_3
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
IP
IP/VREF_3
VCCO_3
VCCO_3
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
DS312-4 (v1.1) March 21, 2005
Advance Product Specification
www.xilinx.com
Pinout Descriptions
TQ144 Pin
P17
P16
P21
P20
P23
P22
P26
P25
P33
P32
P35
P34
P6
P10
P18
P24
P29
P36
P12
P13
P28
P11
P19
P27
P37
P46
P55
P61
P73
P90
P99
P118
P127
P133
Type
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
I/O
I/O
I/O
I/O
I/O
I/O
INPUT
100E: I/O
250E: INPUT
INPUT
INPUT
100E: I/O
250E: INPUT
INPUT
VREF
VCCO
VCCO
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
17