XC3S100E Datasheet, PDF (157/193 Pages) Xilinx, Inc – DC and Switching Characteristics

Pinout Descriptions
R
User I/Os by Bank
Table 20, Table 21, and Table 22 indicate how the available
user-I/O pins are distributed between the four I/O banks on
the FT256 package.
The XC3S250E FPGA in the FT256 package has 18 uncon-
nected balls, labeled with an “N.C.” type. These pins are
also indicated with the black diamond ( ) symbol in
Figure 7.
Table 20: User I/Os Per Bank on XC3S250E in the FT256 Package
Package
Maximum
Edge
I/O Bank
I/O
I/O
All Possible I/O Pins by Type
INPUT
DUAL
VREF
GCLK
Top
0
44
20
10
1
5
8
Right
1
42
10
7
21
4
0
Bottom
2
44
8
9
24
3
0
Left
3
42
24
7
0
3
8
TOTAL
172
62
33
46
15
16
Table 21: User I/Os Per Bank on XC3S500E in the FT256 Package
Package
Maximum
Edge
I/O Bank
I/O
I/O
All Possible I/O Pins by Type
INPUT
DUAL
VREF
Top
0
46
22
10
1
5
Right
1
48
15
7
21
5
Bottom
2
48
11
9
24
4
Left
3
48
28
7
0
5
TOTAL
190
76
33
46
19
GCLK
8
0
0
8
16
Table 22: User I/Os Per Bank on XC3S1200E in the FT256 Package
Package
Maximum
Edge
I/O Bank
I/O
I/O
All Possible I/O Pins by Type
INPUT
DUAL
VREF
Top
0
46
24
8
1
5
Right
1
48
14
8
21
5
Bottom
2
48
13
7
24
4
Left
3
48
27
8
0
5
TOTAL
190
78
31
46
19
GCLK
8
0
0
8
16
36
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DS312-4 (v1.1) March 21, 2005
Advance Product Specification