XC3S100E Datasheet, PDF (53/193 Pages) Xilinx, Inc – DC and Switching Characteristics

Functional Description
R
a. CLKOUT_PHASE_SHIFT = NONE
CLKIN
CLKFB
b. CLKOUT_PHASE_SHIFT = FIXED
CLKIN
Shift Range over all P Values:
CLKFB
–255
0
+255
P
512 ^{* TCLKIN}
c. CLKOUT_PHASE_SHIFT = VARIABLE
CLKIN
Shift Range over all P Values:
CLKFB before
Increment
Shift Range over all N Values:
CLKFB after
Increment
–255
0
+255
P
512
*
T_CLKIN
N
512
*
T_CLKIN
Figure 41: Phase Shifter Waveforms
DS312-2_61_021505
The Variable Phase Mode
The Variable Phase mode dynamically adjusts the fine
phase shift over time using three inputs to the PS compo-
nent (PSEN, PSCLK, and PSINCDEC), as defined in
Table 30.
Table 30: Signals for Variable Phase Mode
Signal
Direction
Description
PSEN⁽¹⁾
Input
Enables PSCLK for variable phase adjustment.
PSCLK⁽¹⁾
Input
Clock to synchronize phase shift adjustment.
PSINCDEC⁽¹⁾
Input
Chooses between increment and decrement for phase adjustment. It is
synchronized to the PSCLK signal.
PSDONE
Output
Goes High to indicate that present phase adjustment is complete and PS component
is ready for next phase adjustment request. It is synchronized to the PSCLK signal.
Notes:
1. It is possible to program this input for either a true or inverted polarity.
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DS312-2 (v1.1) March 21, 2005
Advance Product Specification