XC3S100E Datasheet, PDF (129/193 Pages) Xilinx, Inc – DC and Switching Characteristics

Pinout Descriptions
R
User I/Os by Bank
Table 8 indicates how the 66 available user-I/O pins are dis-
tributed between the four I/O banks on the VQ100 package.
Table 8: User I/Os Per Bank for XC3S100E and XC3S250E in the VQ100 Package
Package
Maximum
Edge I/O Bank
I/O
I/O
All Possible I/O Pins by Type
INPUT
DUAL
VREF
Top
0
15
5
0
1
1
Right
1
15
6
0
0
1
Bottom
2
19
0
0
18
1
Left
3
17
5
1
2
1
TOTAL
66
16
1
21
4
GCLK
8
8
0
8
24
Footprint Migration Differences
The production XC3S100E and XC3S250E FPGAs have
identical footprints in the VQ100 package. Designs can
migrate between the XC3S100E and XC3S250E without
further consideration.
The pinout changed slightly between the XC3S100E engi-
neering samples and the production devices, as shown in
Table 9. In the engineering samples, the mode select pins
M1 and M0 overlap with two global clock inputs feeding the
bottom-edge global buffers and DCMs. In the production
devices, the mode pins are swapped with parallel mode
data pins, D1 and D2. This way, these two mode pins do not
interfere with global clock inputs.
Table 9: XC3S100E Pinout Changes between
Production Devices and Engineering Samples
VQ100 Pin
XC3S100E
Production
Devices
XC3S100E
Engineering
Samples
P40
D2/GCLK2
M1/GCLK2
P41
D1/GCLK3
M0/GCLK3
P42
M1
D2
P43
M0
D1
8
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DS312-4 (v1.1) March 21, 2005
Advance Product Specification