XC3S100E Datasheet, PDF (66/193 Pages) Xilinx, Inc – DC and Switching Characteristics

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Functional Description
Table 41 shows the default I/O standard setting for the vari-
ous configuration pins during the configuration process. The
configuration interface is designed primarily for 2.5V opera-
tion when the VCCO_2 (and VCCO_1 in BPI mode) con-
nects to 2.5V.
The configuration pins also operate at other voltages by set-
ting VCCO_2 (and VCCO_1 in BPI mode) to either 3.3V or
1.8V. The change on the VCCO supply also changes the I/O
drive characteristics. For example, with VCCO = 3.3V, the
output current when driving High, I_OH, increases to approx-
imately 12 to 16 mA, while the current when driving Low,
I_OL, remains 8 mA. At VCCO = 1.8V, the output current
when driving High, I_OH, decreases slightly to approximately
6 to 8 mA. Again, the current when driving Low, I_OL, remains
8 mA.
Table 41: Default I/O Standard Setting During Configuration (VCCO_2 = 2.5V)
Pin(s)
I/O Standard
Output Drive
All, including CCLK
LVCMOS25
8 mA
Slew Rate
Slow
Master Serial Mode
In Master Serial mode (M[2:0] = <0:0:0>), the Spartan-3E
FPGA configures itself from an attached Xilinx Platform
Flash PROM, as illustrated in Figure 48. The FPGA sup-
plies the CCLK output clock from its internal oscillator to the
attached Platform Flash PROM. In response, the Platform
Flash PROM supplies bit-serial data to the FPGA’s DIN
input and the FPGA accepts this data on each rising CCLK
edge.
+1.2V
VCCINT
P
HSWAP
VCCO_0
Serial Master
Mode
‘0’
M2
‘0’
M1
‘0’
M0
VCCO_2
DIN
CCLK
DOUT
INIT_B
Spartan-3E
V
VCCO_0
V
+2.5V
+2.5V
JTAG
TDI
TMS
TCK
TDO
TDI
TMS
TCK
VCCAUX
TDO
PROG_B
GND
DONE
+2.5V
XCFxxS = +3.3V
XCFxxP = +1.8V
VCCINT
D0
VCCO
CLK
OE/RESET
Platform Flash
XCFxx
CE
CEO
CF
TDI
TMS
TCK
VCCJ
TDO
GND
V
+2.5V
PROG_B
Recommend
open-drain
driver
Figure 48: Master Serial Mode using Platform Flash PROM
DS312-2_44_021405
DS312-2 (v1.1) March 21, 2005
www.xilinx.com
59
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