XC3S100E Datasheet, PDF (39/193 Pages) Xilinx, Inc – DC and Switching Characteristics

Functional Description
R
Table 21: Block RAM Attributes (Continued)
Function
Attribute
Data Output Latch Synchronous
Set/Reset Value
SRVAL (single-port)
SRVAL_A, SRVAL_B
(dual-port)
Data Output Latch Behavior during Write
(see Block RAM Data Operations)
WRITE_MODE
Possible Values
Hex value the width of the chosen port.
WRITE_FIRST, READ_FIRST, NO_CHANGE
Block RAM Data Operations
Writing data to and accessing data from the block RAM are
synchronous operations that take place independently on
each of the two ports. Table 22 describes the data opera-
tions of each port as a result of the block RAM control sig-
nals in their default active-High edges.
The waveforms for the write operation are shown in the top
half of Figure 30, Figure 31, and Figure 32. When the WE
and EN signals enable the active edge of CLK, data at the
DI input bus is written to the block RAM location addressed
by the ADDR lines.
Table 22: Block RAM Function Table
Input Signals
Output Signals
GSR EN SSR WE CLK ADDR DIP DI
DOP
DO
Immediately After Configuration
Loaded During Configuration
X
X
Global Set/Reset Immediately After Configuration
RAM Data
Parity
Data
INITP_xx
INIT_xx
1
X
X
X
X
X
X
X
INIT
INIT
No Chg
No Chg
RAM Disabled
0
0
X
X
X
X
X
X
No Chg
No Chg
No Chg
No Chg
Synchronous Set/Reset
0
1
1
0
↑
X
X
X
SRVAL
SRVAL
No Chg
No Chg
Synchronous Set/Reset During Write RAM
0
1
1
1
↑ addr pdata Data SRVAL
SRVAL
RAM(addr) RAM(addr)
← pdata
← data
Read RAM, no Write Operation
0
1
0
0
↑ addr X
X RAM(pdata) RAM(data)
No Chg
No Chg
Write RAM, Simultaneous Read Operation
0
1
0
1
↑ addr pdata Data
WRITE_MODE = WRITE_FIRST
pdata
data
RAM(addr) RAM(addr)
← pdata
← data
WRITE_MODE = READ_FIRST
RAM(data) RAM(data) RAM(addr) RAM(addr)
← pdata
← pdata
WRITE_MODE = NO_CHANGE
No Chg
No Chg
RAM(addr) RAM(addr)
← pdata
← pdata
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DS312-2 (v1.1) March 21, 2005
Advance Product Specification