XC3S100E Datasheet, PDF (143/193 Pages) Xilinx, Inc – DC and Switching Characteristics

Pinout Descriptions
R
Table 17: PQ208 Package Pinout
Bank
XC3S250E
XC3S500E
Pin Name
PQ208
Pin
Type
1
IO_L09N_1/A5/RHCLK5 P133 RHCLK/DUAL
1
IO_L09P_1/A6/RHCLK4 P132 RHCLK/DUAL
1
IO_L10N_1/A3/RHCLK7 P135 RHCLK/DUAL
1
IO_L10P_1/A4/RHCLK6 P134 RHCLK/DUAL
1
IO_L11N_1/A1
P138
DUAL
1
IO_L11P_1/A2
P137
DUAL
1
IO_L12N_1/A0
P140
DUAL
1
IO_L12P_1
P139
I/O
1
IO_L13N_1
P145
I/O
1
IO_L13P_1
P144
I/O
1
IO_L14N_1
P147
I/O
1
IO_L14P_1
P146
I/O
1
IO_L15N_1/LDC0
P151
DUAL
1
IO_L15P_1/HDC
P150
DUAL
1
IO_L16N_1/LDC2
P153
DUAL
1
IO_L16P_1/LDC1
P152
DUAL
1
IP
P110
INPUT
1
IP
P118
INPUT
1
IP
P124
INPUT
1
IP
P130
INPUT
1
IP
P142
INPUT
1
IP
P148
INPUT
1
IP
P154
INPUT
1
IP/VREF_1
P136
VREF
1
VCCO_1
P114
VCCO
1
VCCO_1
P125
VCCO
1
VCCO_1
P143
VCCO
2
IO/D5
P76
DUAL
2
IO/M1
P84
DUAL
2
IO/VREF_2
P98
VREF
2
IO_L01N_2/INIT_B
P56
DUAL
2
IO_L01P_2/CSO_B
P55
DUAL
2
IO_L03N_2/MOSI/CSI_B P61
DUAL
2
IO_L03P_2/DOUT/BUSY P60
DUAL
Table 17: PQ208 Package Pinout
Bank
XC3S250E
XC3S500E
Pin Name
PQ208
Pin
Type
2
IO_L04N_2
P63
I/O
2
IO_L04P_2
P62
I/O
2
IO_L05N_2
P65
I/O
2
IO_L05P_2
P64
I/O
2
IO_L06N_2
P69
I/O
2
IO_L06P_2
P68
I/O
2
IO_L08N_2/D6/GCLK13 P75 DUAL/GCLK
2
IO_L08P_2/D7/GCLK12 P74 DUAL/GCLK
2
IO_L09N_2/D3/GCLK15 P78 DUAL/GCLK
2
IO_L09P_2/D4/GCLK14 P77 DUAL/GCLK
2
IO_L11N_2/D1/GCLK3
P83 DUAL/GCLK
2
IO_L11P_2/D2/GCLK2
P82 DUAL/GCLK
2
IO_L12N_2/DIN/D0
P87
DUAL
2
IO_L12P_2/M0
P86
DUAL
2
IO_L13N_2
P90
I/O
2
IO_L13P_2
P89
I/O
2
IO_L14N_2/A22
P94
DUAL
2
IO_L14P_2/A23
P93
DUAL
2
IO_L15N_2/A20
P97
DUAL
2
IO_L15P_2/A21
P96
DUAL
2
IO_L16N_2/VS1/A18
P100
DUAL
2
IO_L16P_2/VS2/A19
P99
DUAL
2
IO_L17N_2/CCLK
P103
DUAL
2
IO_L17P_2/VS0/A17
P102
DUAL
2
IP
P54
INPUT
2
IP
P91
INPUT
2
IP
P101
INPUT
2
IP_L02N_2
P58
INPUT
2
IP_L02P_2
P57
INPUT
2
IP_L07N_2/VREF_2
P72
VREF
2
IP_L07P_2
P71
INPUT
2
IP_L10N_2/M2/GCLK1
P81 DUAL/GCLK
2
IP_L10P_2/RDWR_B/
GCLK0
P80 DUAL/GCLK
2
VCCO_2
P59
VCCO
22
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DS312-4 (v1.1) March 21, 2005
Advance Product Specification