XC3S100E Datasheet, PDF (119/193 Pages) Xilinx, Inc – DC and Switching Characteristics

DC and Switching Characteristics
R
Table 18: Timing for the Slave Parallel Configuration Mode (Continued)
Symbol
Description
Hold Times
T_SMCCD
The time from the rising transition at the CCLK pin to the point when data is
last held at the D0-D7 pins
T_SMCCCS
The time from the rising transition at the CCLK pin to the point when a logic
level is last held at the CS_B pin
T_SMWCC
The time from the rising transition at the CCLK pin to the point when a logic
level is last held at the RDWR_B pin
Clock Timing
T_CCH
T_CCL
F_CCPAR
The High pulse width at the CCLK input pin
The Low pulse width at the CCLK input pin
Frequency of the clock
signal at the CCLK input
pin
No bitstream
compression
Not using the BUSY pin⁽²⁾
Using the BUSY pin
With bitstream compression
All Speed Grades
Min
Max Units
0
-
ns
0
-
ns
0
-
ns
5
-
ns
5
-
ns
-
50 MHz
-
66 MHz
-
20 MHz
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 4.
2. In the Slave Parallel mode, it is necessary to use the BUSY pin when the CCLK frequency exceeds this maximum specification.
3. Some Xilinx documents may refer to Parallel modes as "SelectMAP" modes.
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DS312-3 (v1.0) March 1, 2005
Advance Product Specification