XC3S100E Datasheet, PDF (10/193 Pages) Xilinx, Inc – DC and Switching Characteristics

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Functional Description
Input Delay Functions
Each IOB has a programmable delay block that can delay
the input signal from 0 to nominally 4000 ps. In Figure 2, the
signal is first delayed by either 0 or 2000 ps (nominal) and is
then applied to an 8 tap delay line. This delay line has a
nominal value of 250 ps per tap. All 8 taps are available via
a multiplexer for use as an asynchronous input directly into
the FPGA fabric. In this way, the delay is programmable
from 0 to 4000 ps in 250 ps steps. Four of the 8 taps are
also available via a multiplexer to the D inputs of the syn-
chronous storage elements. The delay inserted in the path
to the storage element can be varied from 0 to 4000 ps in
500 ps steps. The first, coarse delay element is common to
both asynchronous and synchronous paths, and must be
either used or not used for both paths.
The delay values are set up in the silicon once at configura-
tion time—they are non-modifiable in device operation.
The primary use for the input delay element is as an ade-
quate delay to ensure that there is no hold time requirement
when using the input flip-flop(s) with a global clock. The
necessary value for this function is chosen by the Xilinx soft-
ware tools and depends on device size. If the design is
using a DCM in the clock path, then the delay element can
be safely set to zero in the user's design, and there is still no
hold time requirement.
Both asynchronous and synchronous values can be modi-
fied by the user, which is useful where extra delay is
required on clock or data inputs, for example, in interfaces to
various types of RAM.
See Module 3 of the Spartan-3E data sheet for exact values
for the delay elements.
Synchronous input (IQ1)
DQ
Synchronous input (IQ2)
DQ
PAD
Asynchronous input (I)
Figure 2: Input Delay Elements
DS312-2_18_022205
DS312-2 (v1.1) March 21, 2005
www.xilinx.com
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