XC3S100E Datasheet, PDF (139/193 Pages) Xilinx, Inc – DC and Switching Characteristics

Pinout Descriptions
R
Table 12: TQ144 Package Pinout (Continued)
Bank
XC3S100E Pin Name
XC3S250E Pin Name
VCCAUX DONE
DONE
VCCAUX PROG_B
PROG_B
VCCAUX TCK
TCK
VCCAUX TDI
TDI
VCCAUX TDO
TDO
VCCAUX TMS
TMS
VCCAUX VCCAUX
VCCAUX
VCCAUX VCCAUX
VCCAUX
VCCAUX VCCAUX
VCCAUX
VCCAUX VCCAUX
VCCAUX
VCCINT VCCINT
VCCINT
VCCINT VCCINT
VCCINT
VCCINT VCCINT
VCCINT
VCCINT VCCINT
VCCINT
TQ144 Pin
P72
P1
P110
P144
P109
P108
P30
P65
P102
P137
P9
P45
P80
P115
User I/Os by Bank
Table 13 and Table 14 indicate how the 108 available
user-I/O pins are distributed between the four I/O banks on
the TQ144 package.
Table 13: User I/Os Per Bank for the XC3S100E in the TQ144 Package
Package
Maximum
Edge
I/O Bank
I/O
I/O
All Possible I/O Pins by Type
INPUT
DUAL
VREF
Top
0
26
9
6
1
2
Right
1
28
0
5
21
2
Bottom
2
26
0
4
20
2
Left
3
28
13
4
0
3
TOTAL
108
22
19
42
9
Type
CONFIG
CONFIG
JTAG
JTAG
JTAG
JTAG
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
GCLK
8
0
0
8
16
Table 14: User I/Os Per Bank for the XC3S250E in TQ144 Package
Package
Maximum
Edge
I/O Bank
I/O
I/O
All Possible I/O Pins by Type
INPUT
DUAL
VREF
Top
0
26
9
6
1
2
Right
1
28
0
5
21
2
Bottom
2
26
0
4
20
2
Left
3
28
11
6
0
3
TOTAL
108
20
21
42
9
GCLK
8
0
0
8
16
18
www.xilinx.com
DS312-4 (v1.1) March 21, 2005
Advance Product Specification