XC3S100E Datasheet, PDF (57/193 Pages) Xilinx, Inc – DC and Switching Characteristics

Functional Description
R
Table 35: Direct Connections from Clock Inputs to DCMs and Associated DCM Location String
Clock Input
XC3S100E
XC3S250E/XC3S500E
XC3S1200E/XC3S1600E
GCLK[3:0]
DCM_X0Y0
DCM_X1Y0
DCM_X2Y0
RHCLK[3:0]
N/A
N/A
DCM_X3Y1
RHCLK[7:4]
N/A
N/A
DCM_X3Y2
GCLK[7:4]
DCM_X0Y1
DCM_X1Y1
DCM_X2Y2
GCLK[11:8]
N/A
DCM_X0Y1
DCM_X1Y3
LHCLK[3:0]
N/A
N/A
DCM_X0Y2
LHCLK[7:4]
N/A
N/A
DCM_X0Y1
GCLK[15:12]
N/A
DCM_X0Y0
DCM_X1Y0
Table 36: Connections from Clock Inputs to BUFGMUX Elements and Associated Quadrant Clock
Quadrant
Clock
Line⁽¹⁾
Left-Half BUFGMUX
Location⁽²⁾ I0 Input I1 Input
Top or Bottom BUFGMUX
Location⁽²⁾ I0 Input
I1 Input
Right-Half BUFGMUX
Location⁽²⁾ I0 Input I1 Input
A
X0Y2
LHCLK7 LHCLK6
X2Y1
GCLK0 or GCLK1 or
GCLK12 GCLK13
X3Y2
RHCLK0 RHCLK1
B
X0Y3
LHCLK6 LHCLK7
X2Y0
GCLK1 or GCLK0 or
GCLK13 GCLK12
X3Y3
RHCLK1 RHCLK0
C
X0Y4
LHCLK5 LHCLK4
X1Y1
GCLK2 or GCLK3 or
GCLK14 GCLK15
X3Y4
RHCLK2 RHCLK3
D
X0Y5
LHCLK4 LHCLK5
X1Y0
GCLK3 or GCLK2 or
GCLK15 GCLK14
X3Y5
RHCLK3 RHCLK2
E
X0Y6
LHCLK3 LHCLK2
X2Y11
GCLK4 or GCLK5 or
GCLK8 GCLK9
X3Y6
RHCLK4 RHCLK5
F
X0Y7
LHCLK2 LHCLK3
X2Y10
GCLK5 or GCLK4 or
GCLK9 GCLK8
X3Y7
RHCLK5 RHCLK4
G
X0Y8
LHCLK1 LHCLK0
X1Y11
GCLK6 or GCLK7 or
GCLK10 GCLK11
X3Y8
RHCLK6 RHCLK7
H
X0Y9
LHCLK0 LHCLK1
X1Y10
GCLK7 or GCLK6 or
GCLK11 GCLK10
X3Y9
RHCLK7 RHCLK6
Notes:
1. See Quadrant Clock Routing for connectivity details for the eight quadrant clocks.
2. See Figure 42 for specific BUFGMUX locations and Figure 44 for information on how BUFGMUX elements drive onto a specific clock line
within a quadrant.
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DS312-2 (v1.1) March 21, 2005
Advance Product Specification