XC3S100E Datasheet, PDF (135/193 Pages) Xilinx, Inc – DC and Switching Characteristics

Pinout Descriptions
R
TQ144: 144-lead Thin Quad Flat
Package
The XC3S100E and the XC3S250E FPGAs are available in
the 144-lead thin quad flat package, TQ144. Both devices
share a common footprint for this package as shown in
Table 12 and Figure 4.
Table 12 lists all the package pins. They are sorted by bank
number and then by pin name of the largest device. Pins
that form a differential I/O pair appear together in the table.
The table also shows the pin number for each pin and the
pin type, as defined earlier.
The TQ144 package only supports 20 address output pins
in the Byte-wide Peripheral Interface (BPI) configuration
mode. In larger packages, there are 24 BPI address out-
puts.
An electronic version of this package pinout table and foot-
print diagram is available for download from the Xilinx web
site at http://www.xilinx.com/bvdocs/publications/s3e_pin.zip.
Pinout Table
Table 12 shows the pinout for production Spartan-3E
FPGAs in the VQ100 package. The XC3S100 engineering
samples have a slightly different pinout, as described in
Table 15.
Table 12: TQ144 Package Pinout
Bank
XC3S100E Pin Name
0
IO
0
IO/VREF_0
0
IO_L01N_0
0
IO_L01P_0
0
IO_L02N_0
0
IO_L02P_0
0
IO_L04N_0/GCLK5
0
IO_L04P_0/GCLK4
0
IO_L05N_0/GCLK7
0
IO_L05P_0/GCLK6
0
IO_L07N_0/GCLK11
0
IO_L07P_0/GCLK10
0
IO_L08N_0/VREF_0
0
IO_L08P_0
0
IO_L09N_0
0
IO_L09P_0
0
IO_L10N_0/HSWAP
0
IO_L10P_0
0
IP
0
IP
0
IP
0
IP
0
IP_L03N_0
0
IP_L03P_0
0
IP_L06N_0/GCLK9
0
IP_L06P_0/GCLK8
XC3S250E Pin Name
IO
IO/VREF_0
IO_L01N_0
IO_L01P_0
IO_L02N_0
IO_L02P_0
IO_L04N_0/GCLK5
IO_L04P_0/GCLK4
IO_L05N_0/GCLK7
IO_L05P_0/GCLK6
IO_L07N_0/GCLK11
IO_L07P_0/GCLK10
IO_L08N_0/VREF_0
IO_L08P_0
IO_L09N_0
IO_L09P_0
IO_L10N_0/HSWAP
IO_L10P_0
IP
IP
IP
IP
IP_L03N_0
IP_L03P_0
IP_L06N_0/GCLK9
IP_L06P_0/GCLK8
TQ144 Pin
P132
P124
P113
P112
P117
P116
P123
P122
P126
P125
P131
P130
P135
P134
P140
P139
P143
P142
P111
P114
P136
P141
P120
P119
P129
P128
Type
I/O
VREF
I/O
I/O
I/O
I/O
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
VREF
I/O
I/O
I/O
DUAL
I/O
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
GCLK
GCLK
14
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DS312-4 (v1.1) March 21, 2005
Advance Product Specification