XC3S100E Datasheet, PDF (82/193 Pages) Xilinx, Inc – DC and Switching Characteristics

R
Functional Description
Table 51: Byte-Wide Peripheral Interface (BPI) Connections (Continued)
Pin Name FPGA Direction
Description
During Configuration
DONE
Open-drain
bidirectional I/O
FPGA Configuration Done. Low
during configuration. Goes High
when FPGA successfully
completes configuration. Requires
external 330 Ω pull-up resistor to
2.5V.
Low indicates that the FPGA is
not yet configured.
PROG_B
Input
Program FPGA. Active Low.
When asserted Low for 300 ns or
longer, forces the FPGA to restart
its configuration process by
clearing configuration memory and
resetting the DONE and INIT_B
pins once PROG_B returns High.
Requires external 4.7 kΩ pull-up
resistor to 2.5V. If driving
externally, use an open-drain or
open-collector driver.
Must be High to allow
configuration to start.
After Configuration
Pulled High via external
pull-up. When High,
indicates that the FPGA
successfully configured.
Drive PROG_B Low and
release to reprogram
FPGA. Hold PROG_B to
force FPGA I/O pins into
Hi-Z, allowing direct
programming access to
Flash PROM pins.
Voltage Compatibility
V _{The FPGA’s parallel Flash interface signals are within}
I/O Banks 1 and 2. The majority of parallel Flash PROMs
use a single 3.3V supply voltage. Consequently, in most
cases, the FPGA’s VCCO_1 and VCCO_2 supply voltages
must also be 3.3V to match the parallel Flash PROM. There
are some 1.8V parallel Flash PROMs available and the
FPGA interfaces with these devices if the VCCO_1 and
VCCO_2 supplies are also 1.8V.
Supported Parallel NOR Flash PROM Densities
Table 52 indicates the smallest usable parallel Flash PROM
to program a single Spartan-3E FPGA. Parallel Flash den-
sity is specified in bits but addressed as bytes. The FPGA
presents up to 24 address lines during configuration but not
all are required for single FPGA applications. Table 52
shows the minimum required number of address lines
between the FPGA and parallel Flash PROM. The actual
number of address line required depends on the density of
the attached parallel Flash PROM.
A multiple-FPGA daisy-chained application requires a par-
allel Flash PROM large enough to contain the sum of the
FPGA file sizes. An application may also use a larger-den-
sity parallel Flash PROM to hold additional data beyond just
FPGA configuration data. For example, the parallel Flash
PROM could also contain the application code for a Micro-
Blaze RISC processor core implemented within the Spar-
tan-3E FPGA. After configuration, the MicroBlaze processor
could execute directly from external Flash or could copy the
code to other, faster system memory before executing the
code.
Table 52: Number of Bits to Program a Spartan-3E FPGA and Smallest Parallel Flash PROM
Device
Uncompressed
File Sizes (bits)
Smallest Usable Parallel
Flash PROM
Minimum Required Address
Lines
XC3S100E
581,344
1 Mbit
A[16:0]
XC3S250E
1,352,192
2 Mbit
A[17:0]
XC3S500E
2,267,136
4 Mbit
A[18:0]
XC3S1200E
3,832,320
4 Mbit
A[18:0]
XC3S1600E
5,957,760
8 Mbit
A[19:0]
CCLK Frequency
In BPI mode, the FPGA’s internal oscillator generates the
configuration clock frequency that controls all the interface
timing. The FPGA starts configuration at its lowest fre-
quency and increases its frequency for the remainder of the
configuration process if so specified in the configuration bit-
stream. The maximum frequency is specified using the
ConfigRate bitstream generator option. Table 53 shows the
maximum ConfigRate settings, approximately equal to
MHz, for various PROM read access times. Despite using
slower ConfigRate settings, BPI mode is equally fast as the
other configuration modes. In BPI mode, data is accessed
DS312-2 (v1.1) March 21, 2005
www.xilinx.com
75
Advance Product Specification