XC3S100E Datasheet, PDF (102/193 Pages) Xilinx, Inc – DC and Switching Characteristics

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Functional Description
Powering Spartan-3E FPGAs
Voltage Supplies
Like Spartan-3 FPGAs, Spartan-3E FPGAs have multiple
voltage supply inputs, as shown in Table 58. There are two
supply inputs for internal logic functions, V_CCINT and
V_CCAUX. Each of the four I/O banks has a separate V_CCO
supply input that powers the output buffers within the asso-
ciated I/O bank. All of the V_CCO connections to a specific I/O
bank must be connected and must connect to the same
voltage.
Table 58: Spartan-3E Voltage Supplies
Supply
Input
Description
Nominal Supply
Voltage
VCCINT Internal core supply voltage. Supplies all internal logic functions such as
CLBs, block RAM, multipliers, etc. Input to Power-On Reset (POR) circuit.
1.2V
VCCAUX
Auxiliary supply voltage. Supplies Digital Clock Managers (DCMs),
differential drivers, dedicated configuration pins, JTAG interface. Input to
Power-On Reset (POR) circuit.
2.5V
VCCO_0 Supplies the output buffers in I/O Bank 0, the bank along the top edge of the Selectable, 3.3V, 3.0V,
FPGA.
2.5V, 1.8, 1.5V, or 1.2V.
VCCO_1
Supplies the output buffers in I/O Bank 1, the bank along the right edge of the
FPGA. In Byte-Wide Peripheral Interface (BPI) Parallel Flash Mode,
connects to the save voltage as the Flash PROM.
Selectable, 3.3V, 3.0V,
2.5V, 1.8, 1.5V, or 1.2V.
VCCO_2
Supplies the output buffers in I/O Bank 2 the bank along the bottom edge of
the FPGA. Connects to the same voltage as the FPGA configuration source.
Input to Power-On Reset (POR) circuit.
Selectable, 3.3V, 3.0V,
2.5V, 1.8, 1.5V, or 1.2V.
VCCO_3 Supplies the output buffers in I/O Bank 0, the bank along the top edge of the Selectable, 3.3V, 3.0V,
FPGA.
2.5V, 1.8, 1.5V, or 1.2V.
In a 3.3V-only application, all four V_CCO supplies connect to
3.3V. However, Spartan-3E FPGAs provide the ability to
bridge between different I/O voltages and standards by
applying different voltages to the V_CCO inputs of different
banks. Refer to I/O Banking Rules for which I/O standards
can be intermixed within a single I/O bank.
Each I/O bank also has an separate, optional input voltage
reference supply, called VREF. If the I/O bank includes an
I/O standard that requires a voltage reference such as
HSTL or SSTL, then all VREF pins within the I/O bank must
be connected to the same voltage.
Voltage Regulators
Various power supply manufacturers offer complete power
solutions for Xilinx FPGAs including some with integrated
three-rail regulators specifically designed for Spartan-3 and
Spartan-3E FPGAs. The Xilinx Power Corner web site pro-
vides links to vendor solution guides and Xilinx power esti-
mation and analysis tools.
Power Distribution System (PDS) Design and
Decoupling/Bypass Capacitors
Good power distribution system (PDS) design is important
for all FPGA designs, but especially so for high performance
applications, greater than 100 MHz. Proper design results in
better overall performance, lower clock and DCM jitter, and
a generally more robust system. Before designing the
printed circuit board (PCB) for the FPGA design, please
review XAPP623: "Power Distribution System (PDS)
Design: Using Bypass/Decoupling Capacitors".
DS312-2 (v1.1) March 21, 2005
www.xilinx.com
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