XC3S100E Datasheet, PDF (90/193 Pages) Xilinx, Inc – DC and Switching Characteristics

R
Functional Description
V
Intelligent
Download Host
Configuration
Memory
Source
• Internal memory
• Disk drive
• Over network
• Over RF link
VCC
DATA[7:0]
BUSY
SELECT
READ/WRITE
CLOCK
PROG_B
DONE
INIT_B
GND
• Microcontroller
• Processor
• Tester
+1.2V
+1.2V
D[7:0]
CCLK
P
Slave
Parallel
Mode
‘1’
‘1’
‘0’
‘0’
VCCINT
HSWAP
VCCO_0
VCCO_1
LDC0
LDC1
HDC
LDC2
VCCO_2
M2
M1
M0
Spartan-3E
D[7:0] _FPGA
BUSY
CSI_B
CSO_B
RDWR_B
INIT_B
CCLK
TDI
TMS
TCK
VCCAUX
TDO
PROG_B
GND
DONE
VCCO_0
VCCO_1
V
V
P
Slave
Parallel
Mode
‘1’
‘1’
‘0’
‘0’
VCCINT
HSWAP
VCCO_0
VCCO_1
LDC0
LDC1
HDC
LDC2
VCCO_2
M2
M1
M0
Spartan-3E
D[7:0] _FPGA
BUSY
CSI_B
CSO_B
RDWR_B
INIT_B
CCLK
+2.5V
+2.5V
TDI
TMS
TCK
VCCAUX
TDO
PROG_B
DONE
GND
VCCO_0
VCCO_1
V
CSO_B
+2.5V
PROG_B
Recommend
open-drain 2.5V
driver JTAG
TDI
TMS
TCK
TDO
Figure 59: Daisy-Chaining using Slave Parallel Mode
PROG_B
DONE
INIT_B
TMS
TCK
DS312-2_53_022305
Slave Serial Mode
In Slave Serial mode (M[2:0] = <1:1:1>), an external host
such as a microprocessor or microcontroller writes serial
configuration data into the FPGA, using the synchronous
serial interface shown in Figure 60. The serial configuration
data is presented on the FPGA’s DIN input pin with suffi-
cient setup time before each rising edge of the externally
generated CCLK clock input.
The intelligent host starts the configuration process by puls-
ing PROG_B and monitoring that the INIT_B pin goes High,
indicating that the FPGA is ready to receive its first data.
The host then continues supplying data and clock signals
until either the DONE pin goes High, indicating a successful
configuration, or until the INIT_B pin goes Low, indicating a
configuration error. The configuration process requires
more clock cycles than indicated from the configuration file
size. Additional clocks are required during the FPGA’s
start-up sequence, especially if the FPGA is programmed to
wait for selected Digital Clock Managers (DCMs) to lock to
their respective clock inputs (see Start-Up, page 91).
DS312-2 (v1.1) March 21, 2005
www.xilinx.com
83
Advance Product Specification