XC3S100E Datasheet, PDF (9/193 Pages) Xilinx, Inc – DC and Switching Characteristics

Functional Description
R
T
T1
TCE
T2
ODDROUT1
O1
ODDRIN1
OTCLK1
OCE
O2
ODDRIN2
OTCLK2
ODDROUT2
TFF1
D
Q
CE
CK
SR REV
DDR
MUX
D
Q
TFF2
CE
CK
SR REV
Three-state Path
D
CE
CK
SR
OFF1
Q
REV
DDR
MUX
D
CE
CK
SR
Q
OFF2
REV
Program-
mable
Output
Driver
Output Path
VCCO
Pull-Up
Pull-
Down
ESD
I/O
Pin
ESD
Keeper
Latch
I
IQ1
IDDRIN1
IDDRIN2
ICLK1
ICE
IQ2
ICLK2
SR
REV
Programmable
Delay
D
Q
CE
IFF1
CK
SR REV
D
Q
IFF2
CE
CK
SR REV
Input Path
LVCMOS, LVTTL, PCI
Single-ended Standards
using VREF
Differential Standards
Notes:
1. All IOB signals communicating with the FPGA’s internal logic have the option of inverting polarity inside the IOB.
2. Signals shown with dashed lines connect to the adjacent IOB in a differential pair only, not to the FPGA fabric.
Figure 1: Simplified IOB Diagram
VREF
Pin
I/O Pin
from
Adjacent
IOB
DS312-2_19_030105
2
www.xilinx.com
DS312-2 (v1.1) March 21, 2005
Advance Product Specification