XC3S100E Datasheet, PDF (117/193 Pages) Xilinx, Inc – DC and Switching Characteristics

DC and Switching Characteristics
R
PROG_B
(Input)
INIT_B
(Open-Drain)
CCLK
(Input/Output)
DIN
(Input)
DOUT
(Output)
T_DCC
T_CCD
Bit 0
Bit 1
T_CCL
T_CCH
1/F_CCSER
Bit n Bit n+1
T_CCO
Bit n-64 Bit n-63
Figure 4: Waveforms for Master and Slave Serial Configuration
DS099-3_04_071604
Table 17: Timing for the Master and Slave Serial Configuration Modes
Symbol
Description
Clock-to-Output Times
T_CCO
The time from the falling transition on the CCLK pin to data
appearing at the DOUT pin
Setup Times
T_DCC
The time from the setup of data at the DIN pin to the rising transition
at the CCLK pin
Hold Times
T_CCD
The time from the rising transition at the CCLK pin to the point when
data is last held at the DIN pin
Clock Timing
T_CCH
T_CCL
F_CCSER
The High pulse width at the CCLK input pin
The Low pulse width at the CCLK input pin
Frequency of the clock signal at No bitstream compression
the CCLK input pin
With bitstream compression
∆F_CCSER Variation from the CCLK output frequency set using the ConfigRate
BitGen option
Slave/
Master
Both
Both
Both
Slave
Master
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 4.
2. For serial configuration with a daisy-chain of multiple FPGAs, the maximum limit is 25 MHz.
All Speed Grades
Min
Max Units
1.5
12.0
ns
10.0
-
ns
0
-
ns
5.0
5.0
-
-
–50%
-
-
66⁽²⁾
20
+50%
ns
ns
MHz
MHz
-
14
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DS312-3 (v1.0) March 1, 2005
Advance Product Specification