XC3S100E Datasheet, PDF (78/193 Pages) Xilinx, Inc – DC and Switching Characteristics

R
Functional Description
+1.2V
VCCINT
P
HSWAP
VCCO_0
SPI Mode
‘0’
M2
‘0’
M1
‘1’
M0
VCCO_2
MOSI
DIN
CSO_B
Variant Select
‘1’
S
‘1’
+2.5V
JTAG
TDI
TMS
TCK
TDO
Spartan-3E
VS2 _FPGA
VS1
VS0
CCLK
DOUT
INIT_B
TDI
TMS
TCK
VCCAUX
TDO
PROG_B
GND
DONE
VCCO_0
I
+3.3V
W
‘1’
+3.3V
SPI
Serial
P
Flash
VCC
DATA_IN
DATA_OUT
SELECT
WR_PROTECT
HOLD
CLOCK
GND
+2.5V
+2.5V +3.3V
+1.2V
P
Slave
Serial
Mode
‘1’
‘1’
‘1’
VCCINT
HSWAP
VCCO_0
VCCO_2
M2
M1
M0
Spartan-3E
FPGA
CCLK
DIN
TDI
TMS
TCK
DOUT
INIT_B
VCCAUX
TDO
PROG_B
DONE
GND
VCCO_0
+3.3V
+2.5V
CCLK
DOUT
PROG_B
Recommend
open-drain
driver
PROG_B
TCK
TMS
DONE
INIT_B
Figure 54: Daisy-Chaining from SPI Flash Mode
DS312-2_48_021405
In-System Programming Support
I _{In a production application, the SPI Flash PROM is usu-}
ally pre-programmed before it is mounted on the printed cir-
cuit board. In-system programming support is available
from some third-party PROM programmers using a socket
adapter with attached wires. To gain access to the SPI
Flash signals, drive the FPGA’s PROG_B input Low with an
open-drain driver. This action places all FPGA I/O pins,
including those attached to the SPI Flash, in high-imped-
ance (Hi-Z). If the HSWAP input is High, the I/Os have
pull-up resistors to the V_CCO input on their respective I/O
bank. The external programming hardware then has direct
access to the SPI Flash pins. The programming access
points are highlighted in the gray box in Figure 50,
Figure 51, and Figure 54.
Byte-Wide Peripheral Interface (BPI) Parallel
Flash Mode
In Byte-wide Peripheral Interface (BPI) mode
(M[2:0] = <0:1:0> or <0:1:1>), a Spartan-3E FPGA config-
ures itself from an industry-standard parallel NOR Flash
PROM, as illustrated in Figure 55. The FPGA generates up
to a 24-bit address lines to access an attached parallel
Flash. Only 20 address lines are generated for Spartan-3E
FPGAs in the TQ144 package. The BPI mode is not avail-
able for Spartan-3E FPGAs in the VQ100 package.
The interface is designed for standard parallel NOR Flash
PROMs and supports both byte-wide (x8) and
byte-wide/halfword (x8/x16) PROMs. The interface does not
support halfword-only (x16) PROMs. The interface works
equally wells with other memories that use a similar inter-
face such as SRAM, NVRAM, EEPROM, EPROM, or
masked ROM but is primarily designed for Flash memory.
There is another type of Flash memory called NAND Flash,
which is commonly used in memory cards for digital cam-
eras, etc. Spartan-3E FPGAs do not configure directly from
NAND Flash memories.
The FPGA’s internal oscillator controls the interface timing
and the FPGA supplies the clock on the CCLK output pin.
However, the CCLK signal is not used in single FPGA appli-
cations. Similarly, the FPGA drives three pins Low during
configuration (LDC[2:0]) and one pin High during configura-
tion (HDC) to the PROM’s control inputs.
DS312-2 (v1.1) March 21, 2005
www.xilinx.com
71
Advance Product Specification