XC3S100E Datasheet, PDF (75/193 Pages) Xilinx, Inc – DC and Switching Characteristics

Functional Description
R
Power-On Precautions if 3.3V Supply is Last in
Sequence
Spartan-3E FPGAs have a built-in power-on reset (POR)
circuit, as shown in Figure 63. The FPGA waits for its three
power supplies — VCCINT, VCCAUX, and VCCO to I/O
Bank 2 (VCCO_2) — to reach their respective power-on
thresholds before beginning the configuration process.
The SPI Flash PROM is powered by the same voltage sup-
ply feeding the FPGA's VCCO_2 voltage input, typically
3.3V. SPI Flash PROMs specify that they cannot be
accessed until their VCC supply reaches its minimum data
sheet voltage, followed by an additional delay. For some
devices, this additional delay is as little as 10 µs as shown in
Table 48. For other vendors, it is as much as 20 ms.
Table 48: Example Minimum Power-On to Select Times for Various SPI Flash PROMs
Vendor
SPI Flash PROM
Part Number
Data Sheet Minimum Time from VCC, min. to Select = Low
Symbol
Value
Units
STMicroelectronics
M25Pxx
T_VSL
10
µs
NexFlash
NX25xx
T_VSL
10
µs
Silicon Storage Technology
SST25LFxx
T_PU-READ
10
µs
Programmable
Microelectronics Corporation
Pm25LVxxx
T_VCS
50
µs
Atmel Corporation
AT45DBxx
20
ms
In many systems, the 3.3V supply feeding the FPGA's
VCCO_2 input is valid before the FPGA's other VCCINT
and VCCAUX supplies, and consequently, there is no issue.
However, if the 3.3V supply feeding the FPGA's VCCO_2
supply is last in the sequence, a potential race occurs
between the FPGA and the SPI Flash PROM, as shown in
Figure 52.
If the FPGA's VCCINT and VCCAUX supplies are already
valid, then the FPGA waits for VCCO_2 to reach its mini-
mum threshold voltage before starting configuration. This
threshold voltage is labeled as V_CCO2T in Module 3 and
ranges from approximately 0.4V to 1.0V, substantially lower
than the SPI Flash PROM's minimum voltage. Once all
three FPGA supplies reach their respective Power On
Reset (POR) thresholds, the FPGA starts the configuration
process and begins initializing its internal configuration
memory. Initialization requires approximately 1 ms (T_POR,
3.3V Supply
minimum in Module 3), after which the FPGA deasserts
INIT_B, selects the SPI Flash PROM, and starts sending
the appropriate read command. The SPI Flash PROM must
be ready for read operations at this time.
If the 3.3V supply is last in the sequence and does not ramp
fast enough, or if the SPI Flash PROM cannot be ready
when required by the FPGA, delay the FPGA configuration
process by holding either the FPGA's PROG_B input or
INIT_B input Low, as highlighted in Figure 51. Release the
FPGA when the SPI Flash PROM is ready. For example, a
simple R-C delay circuit attached to the INIT_B pin forces
the FPGA to wait for a preselected amount of time. Alter-
nately, a Power Good signal from the 3.3V supply or a sys-
tem reset signal accomplishes the same purpose. Use an
open-drain or open-collector output when driving PROG_B
or INIT_B.
SPI Flash cannot be selected
SPI Flash PROM
minimum voltage
FPGA VCCO_2 minimum
Power On Reset Voltage
(V_CCO2T)
(VCCINT, VCCAUX
already valid)
SPI Flash
PROM CS
delay (t_VSL )
SPI Flash available for
read operations
SPI Flash PROM must
be ready for FPGA
access otherwise delay
FPGA configuration
FPGA initializes configuration
memory (T_POR)
Time
FPGA accesses
SPI Flash PROM
DS312-2_50b_022405
Figure 52: SPI Flash PROM/FPGA Power-On Timing if 3.3V Supply is Last in Power-On Sequence
68
www.xilinx.com
DS312-2 (v1.1) March 21, 2005
Advance Product Specification