XC3S100E Datasheet, PDF (79/193 Pages) Xilinx, Inc – DC and Switching Characteristics

Functional Description
R
+1.2V
VCCINT
P
HSWAP
VCCO_0
VCCO_0
I
VCCO_1
V
LDC0
LDC1
HDC
Not available
in VQ100
package
LDC2
A[16:0]
+2.5V
JTAG
TDI
TMS
TCK
TDO
BPI Mode
‘0’
M2
‘1’
M1
A
M0
VCCO_2
D[7:0]
A[23:17]
Spartan-3E _BUSY
FPGA _CCLK
‘0’
CSI_B
CSO_B
‘0’
RDWR_B
INIT_B
TDI
TMS
TCK
VCCAUX
TDO
PROG_B
GND
DONE
V
V
+2.5V
V
VCCO
CE# x8 or
OE# ^x8/x16
WE#
Flash
PROM
BYTE#
D
DQ[15:7]
DQ[7:0]
A[n:0]
GND
+2.5V
PROG_B
Recommend
open-drain
driver
DS312-2_49_022305
Figure 55: Byte-wide Peripheral Interface (BPI) Mode Configured from Parallel NOR Flash PROMs
A _{During configuration, the value of the M0 mode pin}
determines how the FPGA generates addresses, as shown
Table 50. When M0 = 0, the FPGA generates addresses
starting at 0 and increments the address on every falling
CCLK edge. Conversely, when M0 = 1, the FPGA gener-
ates addresses starting at 0xFF_FFFF (all ones) and decre-
ments the address on every falling CCLK edge.
Table 50: BPI Addressing Control
M2 M1 M0 Start Address Addressing
0
0
Incrementing
01
1 0xFF_FFFF Decrementing
This addressing flexibility allows the FPGA to share the par-
allel Flash PROM with an external or embedded processor.
Depending on the specific processor architecture, the pro-
cessor boots either from the top or bottom of memory. The
FPGA is flexible and boots from the opposite end of mem-
ory from the processor. Only the processor or the FPGA can
boot at any given time. The FPGA can configure first, hold-
ing the processor in reset or the processor can boot first,
asserting the FPGA’s PROG_B pin.
The mode select pins, M[2:0], are sampled when the
FPGA’s INIT_B output goes High and must be at defined
logic levels during this time. After configuration, when the
FPGA’s DONE output goes High, the mode pins are avail-
able as full-featured user-I/O pins.
P ^{Similarly, the FPGA’s HSWAP pin must be Low to}
enable pull-up resistors on all user-I/O pins or High to dis-
able the pull-up resistors. The HSWAP control must remain
at a constant logic level throughout FPGA configuration.
After configuration, when the FPGA’s DONE output goes
72
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DS312-2 (v1.1) March 21, 2005
Advance Product Specification