XC3S100E Datasheet, PDF (61/193 Pages) Xilinx, Inc – DC and Switching Characteristics

Functional Description
R
There are four type of general-purpose interconnect avail-
able in each channel, as shown in Figure 47 and described
below.
Long Lines
Each set of 24 long line signals spans the die both horizon-
tally and vertically and connects to one out of every six inter-
connect tiles. At any tile, four of the long lines drive or
receive signals from a switch matrix. Because of their low
capacitance, these lines are well-suited for carrying
high-frequency signals with minimal loading effects (e.g.
skew). If all global clock lines are already committed and
additional clock signals remain to be assigned, long lines
serve as a good alternative.
Hex Lines
Each set of eight hex lines are connected to one out of
every three tiles, both horizontally and vertically. Thirty-two
hex lines are available between any given interconnect tile.
Hex lines are only driven from one end of the route.
Global Controls (STARTUP_SPARTAN3E)
In addition to the general-purpose interconnect, Spartan-3E
FPGAs have two global logic control signals, as described
in Table 37. These signals are available to the FPGA appli-
cation via the STARTUP_SPARTAN3E primitive.
Table 37: Spartan-3E Global Logic Control Signals
Global
Control Input
Description
GSR
When driven High, asynchronously
places all registers and flip-flops in their
initial state (see Initialization, page 24).
Asserted automatically during the FPGA
configuration process (see Start-Up,
page 91).
GTS
When driven High, asynchronously
forces all I/O pins to a high-impedance
state (Hi-Z, three-state).
Double Lines
Each set of eight double lines are connected to every other
tile, both horizontally and vertically. in all four directions.
Thirty-two double lines available between any given inter-
connect tile. Double lines are more connections and more
flexibility, compared to long line and hex lines.
Direct Connections
Direct connect lines route signals to neighboring tiles: verti-
cally, horizontally, and diagonally. These lines most often
drive a signal from a "source" tile to a double, hex, or long
line and conversely from the longer interconnect back to a
direct line accessing a "destination" tile.
The Global Set/Reset (GSR) signal replaces the global
reset signal included in many ASIC-style designs. Use the
GSR control instead of a separate global reset signal in the
design to free up CLB inputs, resulting in a smaller, more
efficient design. Similarly, the GSR signal is asserted auto-
matically during the FPGA configuration process, guaran-
teeing that the FPGA starts-up in a known state.
The STARTUP_SPARTAN3E primitive also includes two
other signals used specifically during configuration. The
MBT signals are for Dynamically Loading Multiple Con-
figuration Images Using MultiBoot Option, page 78. The
CLK input is an alternate clock for configuration Start-Up,
page 91.
Horizontal and
24
Vertical Long Lines
(horizontal channel
shown as an example)
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
6
6
6
6
6
DS312-2_10_022305
Horizontal and
8
Vertical Hex Lines
(horizontal channel
shown as an example)
CLB
CLB
CLB
CLB
CLB
CLB
CLB
Figure 47: Interconnect Types between Two Adjacent Interconnect Tiles
DS312-2_11_020905
54
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DS312-2 (v1.1) March 21, 2005
Advance Product Specification