XC3S100E Datasheet, PDF (67/193 Pages) Xilinx, Inc – DC and Switching Characteristics

Functional Description
R
The mode select pins, M[2:0], must all be Low when sam-
pled, when the FPGA’s INIT_B output goes High. After con-
figuration, when the FPGA’s DONE output goes High, the
mode select pins are available as full-featured user-I/O pins.
P _{Similarly, the FPGA’s HSWAP pin must be Low to}
enable pull-up resistors on all user-I/O pins during configu-
ration or High to disable the pull-up resistors. The HSWAP
control must remain at a constant logic level throughout
FPGA configuration. After configuration, when the FPGA’s
DONE output goes High, the HSWAP pin is available as
full-featured user-I/O pin and is powered by the VCCO_0
supply.
The FPGA's DOUT pin is used in daisy-chain applications,
described later. In a single-FPGA application, the FPGA’s
DOUT pin is not used but is actively driving during the con-
figuration process.
Table 42: Serial Master Mode Connections
Pin Name FPGA Direction
Description
During Configuration
After Configuration
HSWAP
P
Input
User I/O Pull-Up Control. When Low
during configuration, enables pull-up
resistors in all I/O pins to respective I/O
bank V_CCO input.
0: Pull-ups during configuration
1: No pull-ups
Drive at valid logic level
throughout configuration.
User I/O
M[2:0]
Input
Mode Select. Selects the FPGA
configuration mode.
M2 = 0, M1 = 0, M0 = 0.
Sampled when INIT_B goes
High.
User I/O
DIN
Input
Serial Data Input.
Receives serial data from
PROM’s D0 output.
User I/O
CCLK
Output
Configuration Clock. Generated by
FPGA internal oscillator. Frequency
controlled by ConfigRate bitstream
generator option. If CCLK PCB trace is
long or has multiple connections,
terminate this output to maintain signal
integrity.
Drives PROM’s CLK clock
input.
User I/O
DOUT
Output
Serial Data Output.
Actively drives. Not used in
single-FPGA designs. In a
daisy-chain configuration,
this pin connects to DIN input
of the next FPGA in the chain.
User I/O
INIT_B
Open-drain
bidirectional I/O
Initialization Indicator. Active Low. Goes
Low at start of configuration during
Initialization memory clearing process.
Released at end of memory clearing,
when mode select pins are sampled.
Requires external 4.7 kΩ pull-up resistor
to VCCO_2.
Connects to PROM’s
OE/RESET input. FPGA
clears PROM’s address
counter at start of
configuration, enables
outputs during configuration.
PROM also holds FPGA in
Initialization state until PROM
reaches Power-On Reset
(POR) state. If CRC error
detected during
configuration, FPGA drives
INIT_B Low.
User I/O
60
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DS312-2 (v1.1) March 21, 2005
Advance Product Specification