XC3S100E Datasheet, PDF (28/193 Pages) Xilinx, Inc – DC and Switching Characteristics

R
Functional Description
COUT
G[4:1]
G1 G2
1
A[4:1]
G-LUT
D
CYSELG
CY0G
CYMUXG
XORG
YB
Y
YQ
FFY
BY
F[4:1]
GAND
1
0
1
4
A[4:1]
F1 F2
F-LUT
CYSELF
CYMUXF
D
CY0F
XORF
XB
X
XQ
FFX
FAND
CYINIT
1
0
BX
CIN
Figure 19: Carry Logic
DS312-2_14_021305
Table 11: Carry Logic Functions
Function
Description
CYINIT
Initializes carry chain for a slice. Fixed selection of:
• CIN carry input from the slice below
• BX input
CY0F
Carry generation for bottom half of slice. Fixed selection of:
• F1 or F2 inputs to the LUT (both equal 1 when a carry is to be generated)
• FAND gate for multiplication
• BX input for carry initialization
• Fixed "1" or "0" input for use as a simple Boolean function
CY0G
Carry generation for top half of slice. Fixed selection of:
• G1 or G2 inputs to the LUT (both equal 1 when a carry is to be generated)
• GAND gate for multiplication
• BY input for carry initialization
• Fixed "1" or "0" input for use as a simple Boolean function
CYMUXF
Carry generation or propagation mux for bottom half of slice. Dynamic selection via CYSELF of:
• CYINIT carry propagation (CYSELF = 1)
• CY0F carry generation (CYSELF = 0)
DS312-2 (v1.1) March 21, 2005
www.xilinx.com
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Advance Product Specification