XC3S100E Datasheet, PDF (68/193 Pages) Xilinx, Inc – DC and Switching Characteristics

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Functional Description
Table 42: Serial Master Mode Connections (Continued)
Pin Name FPGA Direction
Description
During Configuration
After Configuration
DONE
Open-drain
bidirectional I/O
FPGA Configuration Done. Low during
configuration. Goes High when FPGA
successfully completes configuration.
Requires external 330 Ω pull-up resistor
to 2.5V.
Connects to PROM’s
chip-enable (CE) input.
Enables PROM during
configuration. Disables
PROM after configuration.
Pulled High via
external pull-up.
When High, indicates
that the FPGA
successfully
configured.
PROG_B
Input
Program FPGA. Active Low. When
asserted Low for 300 ns or longer, forces
the FPGA to restart its configuration
process by clearing configuration
memory and resetting the DONE and
INIT_B pins once PROG_B returns High.
Requires external 4.7 kΩ pull-up resistor
to 2.5V. If driving externally, use an
open-drain or open-collector driver.
Must be High during
configuration to allow
configuration to start.
Connects to PROM’s CF pin,
allowing JTAG PROM
programming algorithm to
reprogram the FPGA.
Drive PROG_B Low
and release to
reprogram FPGA.
Voltage Compatibility
The PROM’s V_CCINT supply must be either 3.3V for the
serial XCFxxS Platform Flash PROMs or 1.8V for the
serial/parallel XCFxxP PROMs.
V _{The FPGA’s VCCO_2 supply input and the Platform}
Flash PROM’s V_CCO supply input must be the same volt-
age, ideally +2.5V. Both devices also support 1.8V and 3.3V
interfaces but the FPGA’s PROG_B and DONE pins require
special attention as they are powered by the FPGA’s
VCCAUX supply, nominally 2.5V. See application note
XAPP453: "The 3.3V Configuration of Spartan-3 FPGAs"
for additional information.
Supported Platform Flash PROMs
Table 43 shows the smallest available Platform Flash
PROM to program a single Spartan-3E FPGA. A multi-
ple-FPGA daisy-chain application requires a Platform Flash
PROM large enough to contain the sum of the various
FPGA file sizes.
Table 43: Number of Bits to Program a Spartan-3E
FPGA and Smallest Platform Flash PROM
Device
Number of
Configuration
Bits
Smallest Available
Platform Flash
XC3S100E
581,344
XCF01S
XC3S250E
1,352,192
XCF02S
XC3S500E
2,267,136
XCF04S
XC3S1200E
3,832,320
XCF04S
XC3S1600E
5,957,760
XCF08P
or 2 x XCF04S
The XC3S1600E requires an 8 Mbit PROM. There are two
possible solutions. Either use a single 8 Mbit XCF08P par-
allel/serial PROM or cascade two 4 Mbit XCF04S serial
PROMs. The two XCF04S PROMs use a 3.3V V_CCINT sup-
ply while the XCF08P requires a 1.8V V_CCINT supply. If the
board does not already have a 1.8V supply available, the
two cascaded XCF04S PROM solution is recommended.
CCLK Frequency
In Master Serial mode, the FPGA’s internal oscillator gener-
ates the configuration clock frequency. The FPGA provides
this clock on its CCLK output pin, driving the PROM’s CLK
input pin. The FPGA starts configuration at its lowest fre-
quency and increases its frequency for the remainder of the
configuration process if so specified in the configuration bit-
stream. The maximum frequency is specified using the
ConfigRate bitstream generator option. Table 44 shows the
maximum ConfigRate settings, approximately equal to
MHz, for various Platform Flash devices and I/O voltages.
For the serial XCFxxS PROMs, the maximum frequency
also depends on the interface voltage.
Table 44: Maximum ConfigRate Settings for Platform
Flash
Platform Flash
I/O Voltage
Part Number (VCCO_2, VCCO)
Maximum
ConfigRate
Setting
XCF01S
3.3V or 2.5V
25
XCF02S
XCF04S
1.8V
12
XCF08P
XCF16P
3.3V, 2.5V, or 1.8V
25
XCF32P
DS312-2 (v1.1) March 21, 2005
www.xilinx.com
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