XC3S100E Datasheet, PDF (133/193 Pages) Xilinx, Inc – DC and Switching Characteristics

Pinout Descriptions
R
Table 10: CP132 Package Pinout
Bank
XC3S250E
XC3S500E
Pin Name
GND GND
GND GND
VCCAUX DONE
VCCAUX PROG_B
VCCAUX TCK
VCCAUX TDI
VCCAUX TDO
VCCAUX TMS
VCCAUX VCCAUX
VCCAUX VCCAUX
VCCAUX VCCAUX
CP132
Ball
P10
P14
P13
A1
B13
A2
A14
B14
A5
E12
K1
Type
GND
GND
CONFIG
CONFIG
JTAG
JTAG
JTAG
JTAG
VCCAUX
VCCAUX
VCCAUX
Table 10: CP132 Package Pinout
Bank
XC3S250E
XC3S500E
Pin Name
VCCAUX VCCAUX
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
CP132
Ball
P9
A11
D3
D14
K2
L12
P2
Type
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
User I/Os by Bank
Table 20 indicates how the 92 available user-I/O pins are
distributed between the four I/O banks on the CP132 pack-
age.
Table 11: User I/Os Per Bank for the XC3S250E and XC3S500E in the CP132 Package
Package
Maximum
Edge
I/O Bank
I/O
I/O
All Possible I/O Pins by Type
INPUT
DUAL
VREF
Top
0
22
11
0
1
2
Right
1
23
0
0
21
2
Bottom
2
26
0
0
24
2
Left
3
21
11
0
0
2
TOTAL
92
22
0
46
8
GCLK
8
0
0
8
16
Footprint Migration Differences
The production XC3S250E and XC3S500E FPGAs have
identical footprints in the CP132 package. Designs can
migrate between the XC3S250E and XC3S500E without
further consideration.
12
www.xilinx.com
DS312-4 (v1.1) March 21, 2005
Advance Product Specification