XC3S100E Datasheet, PDF (20/193 Pages) Xilinx, Inc – DC and Switching Characteristics

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Functional Description
Configurable Logic Block (CLB) and
Slice Resources
CLB Overview
The Configurable Logic Blocks (CLBs) constitute the main
logic resource for implementing synchronous as well as
combinatorial circuits. Each CLB contains four slices, and
each slice contains two Look-Up Tables (LUTs) to imple-
ment logic and two dedicated storage elements that can be
used as flip-flops or latches. The LUTs can be used as a
16x1 memory (RAM16) or as a 16-bit shift register (SRL16),
and additional multiplexers and carry logic simplify wide
logic and arithmetic functions. Most general-purpose logic
in a design is automatically mapped to the slice resources in
the CLBs. Each CLB is identical, and the Spartan-3E family
CLB structure is identical to that for the Spartan-3 family.
CLB Array
The CLBs are arranged in a regular array of rows and col-
umns as shown in Figure 11.
Each density varies by the number of rows and columns of
CLBs (see Table 6).
X0Y3 X1Y3 X2Y3 X3Y3
X0Y2 X1Y2 X2Y2 X3Y2
Spartan-3E
FPGA
X0Y1 X1Y1 X2Y1 X3Y1
X0Y0 X1Y0 X2Y0 X3Y0
IOBs
CLB
Slice
Figure 11: CLB Locations
DS312-2_31_021205
Table 6: Spartan-3E CLB Resources
Device
CLB
CLB
CLB
Rows Columns Total⁽¹⁾
XC3S100E
22
16
240
XC3S250E
34
26
612
XC3S500E
46
34
1164
XC3S1200E 60
46
2168
XC3S1600E 76
58
3688
Slices
960
2448
4656
8672
14752
LUTs /
Flip-Flops
1920
4896
9312
17344
29504
Equivalent
Logic Cells
2160
5508
10476
19512
33192
RAM16 /
SRL16
960
2448
4656
8672
14752
Distributed
RAM Bits
15360
39168
74496
138752
236032
Notes:
1. The number of CLBs is less than the multiple of the rows and columns because the block RAM/multiplier blocks and the DCMs are
embedded in the array (see Module 1, Figure 1).
Slices
Each CLB comprises four interconnected slices, as shown
in Figure 13. These slices are grouped in pairs. Each pair is
organized as a column with an independent carry chain.
The left pair supports both logic and memory functions and
its slices are called SLICEM. The right pair supports logic
only and its slices are called SLICEL. Therefore half the
LUTs support both logic and memory (including both
RAM16 and SRL16 shift registers) while half support logic
only, and the two types alternate throughout the array col-
umns. The SLICEL reduces the size of the CLB and lowers
the cost of the device, and can also provide a performance
advantage over the SLICEM.
DS312-2 (v1.1) March 21, 2005
www.xilinx.com
13
Advance Product Specification