XC3S100E Datasheet, PDF (60/193 Pages) Xilinx, Inc – DC and Switching Characteristics

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Functional Description
Interconnect
Interconnect is the programmable network of signal path-
ways between the inputs and outputs of functional elements
within the FPGA, such as IOBs, CLBs, DCMs, block RAM,
etc.
Interconnect, also called routing, is segmented for optimal
connectivity. Functionally, interconnect resources are identi-
cal to that of the Spartan-3 architecture. There are four
kinds of interconnects: long lines, hex lines, double lines,
and direct lines. The Xilinx Place and Route (PAR) software
exploits the rich interconnect array to deliver optimal system
performance and the fastest compile times.
The switch matrix connects to the different kinds of intercon-
nects across the device. An interconnect tile, shown in
Figure 45, is defined as a single switch matrix connected to
a functional element, such as a CLB, IOB, or DCM. If a func-
tional element spans across multiple switch matrices such
as the block RAM or multipliers, then an interconnect tile is
defined by the number of switch matrices connected to that
functional element. A Spartan-3E device can be repre-
sented as an array of interconnect tiles where interconnect
resources are for the channel between any two adjacent
interconnect tile rows or columns as shown in Figure 46.
Switch
Matrix
CLB
Switch
Matrix
Switch
Matrix
IOB
Switch
Matrix
DCM
Switch
Matrix
Switch
Matrix
Switch
Matrix
18Kb
Block
RAM
MULT
18 x 18
DS312_08_020905
Figure 45: Four Types of Interconnect Tiles (CLBs, IOBs, DCMs, and Block RAM/Multiplier)
Switch
Matrix
IOB
Switch
Matrix
IOB
Switch
Matrix
IOB
Switch
Matrix
IOB
Switch
Matrix
Switch
Matrix
IOB
Switch
Matrix
CLB
Switch
Matrix
CLB
Switch
Matrix
CLB
Switch
Matrix
Switch
Matrix
IOB
Switch
Matrix
CLB
Switch
Matrix
CLB
Switch
Matrix
CLB
Switch
Matrix
Switch
Matrix
IOB
Switch
Matrix
CLB
Switch
Matrix
CLB
Switch
Matrix
CLB
Switch
Matrix
Switch
Matrix
IOB
Switch
Matrix
CLB
Switch
Matrix
CLB
Switch
Matrix
CLB
Switch
Matrix
Figure 46: Array of Interconnect Tiles in Spartan-3E FPGA
DS312_09_020905
DS312-2 (v1.1) March 21, 2005
www.xilinx.com
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