XC3S100E Datasheet, PDF (73/193 Pages) Xilinx, Inc – DC and Switching Characteristics

Functional Description
R
Table 46: SPI Flash PROM Connections and Pin Naming (Continued)
SPI Flash Pin
RESET
(see Figure 51)
RDY/BUSY
(see Figure 51)
FPGA Connection
Only applicable to Atmel DataFlash. Not
required for FPGA configuration but must be
High during configuration. Optional
connection to FPGA user I/O after
configuration. Do not connect to FPGA’s
PROG_B as this will prevent direct
programming of the DataFlash.
Only applicable to Atmel DataFlash and only
available on certain packages. Not required
for FPGA configuration. Output from
DataFlash PROM. Optional connection to
FPGA user I/O after configuration.
STMicro
N/A
N/A
Silicon
Storage
NexFlash Technology
N/A
N/A
N/A
N/A
Atmel
DataFlash
RESET
RDY/BUSY
The mode select pins, M[2:0], and the variant select pins,
VS[2:0] are sampled when the FPGA’s INIT_B output goes
High and must be at defined logic levels during this time.
After configuration, when the FPGA’s DONE output goes
High, these pins are all available as full-featured user-I/O
pins.
P Similarly, the FPGA’s HSWAP pin must be Low to
enable pull-up resistors on all user-I/O pins or High to dis-
able the pull-up resistors. The HSWAP control must remain
at a constant logic level throughout FPGA configuration.
After configuration, when the FPGA’s DONE output goes
High, the HSWAP pin is available as full-featured user-I/O
pin and is powered by the VCCO_0 supply.
In a single-FPGA application, the FPGA’s DOUT pin is not
used but is actively driving during the configuration process.
Table 47: Serial Peripheral Interface (SPI) Connections
Pin Name FPGA Direction
Description
During Configuration
After Configuration
HSWAP
P
Input
User I/O Pull-Up Control. When
Low during configuration, enables
pull-up resistors in all I/O pins to
respective I/O bank V_CCO input.
0: Pull-ups during configuration
1: No pull-ups
Drive at valid logic level
throughout configuration.
User I/O
M[2:0]
Input
Mode Select. Selects the FPGA
configuration mode.
M2 = 0, M1 = 0, M0 = 1.
Sampled when INIT_B goes
High.
User I/O
VS[2:0]
S
Input
Variant Select. Instructs the
FPGA how to communicate with
the attached SPI Flash PROM.
Must be at the logic levels
shown in Table 45. Sampled
when INIT_B goes High.
User I/O
MOSI
Output
Serial Data Output.
FPGA sends SPI Flash memory
read commands and starting
address to the PROM’s serial
data input.
User I/O
DIN
Input
Serial Data Input.
FPGA receives serial data from User I/O
PROM’s serial data output.
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DS312-2 (v1.1) March 21, 2005
Advance Product Specification