XC3S100E Datasheet, PDF (145/193 Pages) Xilinx, Inc – DC and Switching Characteristics

Pinout Descriptions
Table 17: PQ208 Package Pinout
Bank
XC3S250E
XC3S500E
Pin Name
PQ208
Pin
VCCAUX TDI
P207
VCCAUX TDO
P157
VCCAUX TMS
P155
VCCAUX VCCAUX
P7
VCCAUX VCCAUX
P44
VCCAUX VCCAUX
P66
VCCAUX VCCAUX
P92
VCCAUX VCCAUX
P111
VCCAUX VCCAUX
P149
VCCAUX VCCAUX
P166
VCCAUX VCCAUX
P195
VCCINT VCCINT
P13
Type
JTAG
JTAG
JTAG
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
R
Table 17: PQ208 Package Pinout
Bank
XC3S250E
XC3S500E
Pin Name
PQ208
Pin
VCCINT VCCINT
P67
VCCINT VCCINT
P117
VCCINT VCCINT
P170
Type
VCCINT
VCCINT
VCCINT
User I/Os by Bank
Table 18 indicates how the 158 available user-I/O pins are
distributed between the four I/O banks on the PQ208 pack-
age.
Footprint Migration Differences
The XC3S250E and XC3S500E FPGAs have identical foot-
prints in the PQ208 package. Designs can migrate between
the XC3S250E and XC3S500E without further consider-
ation.
Table 18: User I/Os Per Bank for the XC3S250E and XC3S500E in the PQ208 Package
Package
Maximum
Edge
I/O Bank
I/O
I/O
All Possible I/O Pins by Type
INPUT
DUAL
VREF
Top
0
38
18
6
1
5
Right
1
40
9
7
21
3
Bottom
2
40
8
6
24
2
Left
3
40
23
6
0
3
TOTAL
158
58
25
46
13
GCLK
8
0
0
8
16
24
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DS312-4 (v1.1) March 21, 2005
Advance Product Specification