XC3S100E Datasheet, PDF (118/193 Pages) Xilinx, Inc – DC and Switching Characteristics

R
DC and Switching Characteristics
PROG_B
(Input)
INIT_B
(Open-Drain)
CS_B
(Input)
RDWR_B
(Input)
CCLK
(Input)
T_SMCCW
T_SMCSCC
T_SMDCC
T_SMCCD
T_SMCCCS
T_CCH
T_CCL
T_SMWCC
1/F_CCPAR
D0 - D7
(Inputs)
BUSY
(Output)
High-Z
Byte 0
Byte 1
T_SMCKBY
Byte n
T_SMCKBY
Byte n+1
BUSY
High-Z
DS312-3_02_020805
Notes:
1. It is possible to abort configuration by pulling CS_B Low in a given CCLK cycle, then switching RDWR_B Low or High in any subsequent
cycle for which CS_B remains Low. The RDWR_B pin asynchronously controls the driver impedance of the D0 - D7 bus. When RDWR_B
switches High, be careful to avoid contention on the D0 - D7 bus.
Figure 5: Waveforms for Slave Parallel Configuration
Table 18: Timing for the Slave Parallel Configuration Mode
All Speed Grades
Symbol
Description
Min
Max Units
Clock-to-Output Times
T_SMCKBY
The time from the rising transition on the CCLK pin to a signal transition at the
-
BUSY pin
12.0 ns
Setup Times
T_SMDCC
The time from the setup of data at the D0-D7 pins to the rising transition at the 10.0
-
ns
CCLK pin
T_SMCSCC
The time from the setup of a logic level at the CS_B pin to the rising transition 10.0
-
ns
at the CCLK pin
T_SMCCW(2)
The time from the setup of a logic level at the RDWR_B pin to the rising
transition at the CCLK pin
10.0
-
ns
DS312-3 (v1.0) March 1, 2005
www.xilinx.com
15
Advance Product Specification