XC3S100E Datasheet, PDF (16/193 Pages) Xilinx, Inc – DC and Switching Characteristics

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Functional Description
Table 4: Differential IOSTANDARD Bank Compatibility
Differential
IOSTANDARD
LVDS_25
RSDS_25
MINI_LVDS_25
LVPECL_25
BLVDS_25
V_CCO Supply
2.5V
Input,
On-chip Differential Termination,
Output⁽¹⁾
Input,
On-chip Differential Termination,
Output⁽¹⁾
Input,
On-chip Differential Termination,
Output⁽¹⁾
Input,
On-chip Differential Termination
Input,
On-chip Differential Termination,
Output
3.3V
Input
Input
Input
Input
Input
Input Requirements: V_REF
N/R
(Not Required)
Notes:
1. Each bank can support any two of the following: LVDS_25 outputs, MINI_LVDS_25 outputs, RSDS_25 outputs.
HSTL and SSTL inputs use the Reference Voltage (V_REF) to
bias the input-switching threshold. Once a configuration
data file is loaded into the FPGA that calls for the I/Os of a
given bank to use HSTL/SSTL, a few specifically reserved
I/O pins on the same bank automatically convert to V_REF
inputs. For banks that do not contain HSTL or SSTL, V_REF
pins remain available for user I/Os or input pins.
Differential standards employ a pair of signals, one the
opposite polarity of the other. The noise canceling proper-
ties (for example, Common-Mode Rejection) of these stan-
dards permit exceptionally high data transfer rates. This
subsection introduces the differential signaling capabilities
of Spartan-3E devices.
Each device-package combination designates specific I/O
pairs specially optimized to support differential standards.
Differential pairs can be shown in the Pin and Area Con-
straints Editor (PACE) with the “Show Differential Pairs”
option. A unique L-number, part of the pin name, identifies
the line-pairs associated with each bank (see Module 4).
For each pair, the letters P and N designate the true and
inverted lines, respectively. For example, the pin names
IO_L43P_3 and IO_L43N_3 indicate the true and inverted
lines comprising the line pair L43 on Bank 3.
V_CCO provides current to the outputs and additionally pow-
ers the On-Chip Differential Termination. V_CCO must be
2.5V when using the On-Chip Differential Termination. The
V_REF lines are not required for differential operation.
To further understand how to combine multiple IOSTAN-
DARDs within a bank, refer to IOBs Organized into Banks,
page 10.
On-Chip Differential Termination
Spartan-3E devices provide an on-chip 100Ω differential
termination across the input differential receiver terminals
(See Module 3 for the specific range). The on-chip input dif-
ferential termination in Spartan-3E devices eliminates the
external 100Ω termination resistor commonly found in dif-
ferential receiver circuits. Use differential termination for
LVDS, mini-LVDS, and BLVDS as applications permit.
On-chip Differential Termination is available in banks with
V_CCO = 2.5V and is not supported on dedicated input pins.
Set the DIFF_TERM attribute to TRUE to enable Differential
Termination on a differential I/O pin pair.
The DIFF_TERM attribute uses the following syntax in the
UCF file:
INST <I/O_BUFFER_INSTANTIATION_NAME>
DIFF_TERM = “<TRUE/FALSE>”;
Spartan-3E
Differential
Output
Z0 = 50Ω
Spartan-3E
Differential Input
Spartan-3E
Differential
Output
Z0 = 50Ω
Z0 = 50Ω
Spartan-3E
Differential Input
with On-Chip
Differential
Terminator
Z0 = 50Ω
DS312-2_24_021505
Figure 8: Differential Inputs and Outputs
Pull-Up and Pull-Down Resistors
Pull-up and pull-down resistors inside each IOB optionally
force a floating I/O pin to a determined state. Pull-up and
DS312-2 (v1.1) March 21, 2005
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