XC3S100E Datasheet, PDF (38/193 Pages) Xilinx, Inc – DC and Switching Characteristics

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Functional Description
Table 20: Block RAM Port Signals (Continued)
Signal
Description
Port A
Signal
Name
Port B
Signal
Name
Direction
Function
Data Output Bus DOA
DOB
Output
Data is written to the DO output bus from the RAM location
specified by the address input bus, ADDR. See the DI signal
description for DO port width configurations.
Basic data access occurs on the active edge of the CLK when
WE is inactive and EN is active. The DO outputs mirror the data
stored in the address ADDR memory location. Data access with
WE active if the WRITE_MODE attribute is set to the value:
WRITE_FIRST, which accesses data after the write takes place.
READ_FIRST accesses data before the write occurs. A third
attribute, NO_CHANGE, latches the DO outputs upon the
assertion of WE. See Block RAM Data Operations for details on
the WRITE_MODE attribute.
Parity Data
Output(s)
DOPA
DOPB
Output
Parity outputs represent additional bits included in the data input
path. The number of parity bits ‘p’ included in the DI bus (same
as for the DO bus) depends on a port’s total data path width (w).
See the DIP signal description for configuration details.
Write Enable
WEA
WEB
Input
When asserted together with EN, this input enables the writing of
data to the RAM. When WE is inactive with EN asserted, read
operations are still possible. In this case, a latch passes data
from the addressed memory location to the DO outputs.
Clock Enable
ENA
ENB
Input
When asserted, this input enables the CLK signal to perform
read and write operations to the block RAM. When inactive, the
block RAM does not perform any read or write operations.
Set/Reset
SSRA SSRB
Input
When asserted, this pin forces the DO output latch to the value
of the SRVAL attribute. It is synchronized to the CLK signal.
Clock
CLKA CLKB
Input
This input accepts the clock signal to which read and write
operations are synchronized. All associated port inputs are
required to meet setup times with respect to the clock signal’s
active edge. The data output bus responds after a clock-to-out
delay referenced to the clock signal’s active edge.
Block RAM Attribute Definitions
A block RAM has a number of attributes that control its
behavior as shown in Table 21.
Table 21: Block RAM Attributes
Function
Initial Content for Data Memory, Loaded
during Configuration
Initial Content for Parity Memory, Loaded
during Configuration
Data Output Latch Initialization
Attribute
Possible Values
INITxx (INIT_00 through Each initialization string defines 32 hex values
INIT3F)
of the 16384-bit data memory of the block RAM.
INITPxx (INITP_00
through INITP0F)
Each initialization string defines 32 hex values
of the 2048-bit parity data memory of the block
RAM.
INIT (single-port)
Hex value the width of the chosen port.
INITA, INITB (dual-port)
DS312-2 (v1.1) March 21, 2005
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