XC3S100E Datasheet, PDF (190/193 Pages) Xilinx, Inc – DC and Switching Characteristics

R
Pinout Descriptions
Table 31: FG484 Package Pinout
Bank
XC3S1600E
Pin Name
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
FG484
Ball
K9
K11
K13
L10
L11
L12
L14
M9
M11
M12
Type
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
Table 31: FG484 Package Pinout
Bank
XC3S1600E
Pin Name
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
VCCINT VCCINT
FG484
Ball
M13
N10
N12
N14
P13
Type
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
User I/Os by Bank
Table 32 indicates how the 304 available user-I/O pins are
distributed between the four I/O banks on the FG484 pack-
age.
Table 32: User I/Os Per Bank for the XC3S1600E in the FG484 Package
Package
Maximum
Edge
I/O Bank
I/O
I/O
All Possible I/O Pins by Type
INPUT
DUAL
VREF
Top
0
94
56
22
1
7
Right
1
94
50
16
21
7
Bottom
2
94
45
18
24
7
Left
3
94
63
16
0
7
TOTAL
376
214
72
46
28
Footprint Migration Differences
The XC3S1600E FPGA is the only Spartan-3E device
offered in the FG484 package.
GCLK
8
0
0
8
16
DS312-4 (v1.1) March 21, 2005
www.xilinx.com
69
Advance Product Specification