XC3S100E Datasheet, PDF (86/193 Pages) Xilinx, Inc – DC and Switching Characteristics

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Functional Description
Parallel Flash PROM
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General
FPGA
Application
STARTUP_SPARTAN3E
Parallel Flash PROM
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General
FPGA
Application
GSR
User Area
GTS
MBT
> 300 ns
CLK
Diagnostics
FPGA
Application
User Area
Reconfigure
Diagnostics
FPGA
Application
0
0
First Configuration
Second Configuration
DS312-2_51_021405
Figure 57: Use MultiBoot to Load Alternate Configuration Images
Similarly, the general FPGA application could trigger a
MultiBoot event at any time to reload the diagnostics design.
In another potential application, the initial design loaded into
the FPGA image contains a “golden” or “fail-safe” configura-
tion image, which then communicates with the outside world
and checks for a newer image. If there is a new configura-
tion revision and the new image verifies as good, the
“golden” configuration triggers a MultiBoot event to load the
new image.
When a MultiBoot event is triggered, the FPGA then again
drives its configuration pins as described in Table 51. How-
ever, the FPGA does not assert the PROG_B pin. The sys-
tem design must ensure that no other device drives on
these same pins during the reconfiguration process. The
FPGA’s DONE, LDC[2:0], or HDC pins can temporarily dis-
able any conflicting drivers during reconfiguration.
Slave Parallel Mode
In Slave Parallel mode (M[2:0] = <1:1:0>), an external host
such as a microprocessor or microcontroller writes
byte-wide configuration data into the FPGA, using a typical
peripheral interface as shown in Figure 58.
DS312-2 (v1.1) March 21, 2005
www.xilinx.com
79
Advance Product Specification