XC3S100E Datasheet, PDF (27/193 Pages) Xilinx, Inc – DC and Switching Characteristics

Functional Description
R
The wide multiplexers can be used by the automatic tools or
instantiated in a design using a component such as the
F5MUX. The symbol, signals, and function are described
below. The description is similar for the F6MUX, F7MUX,
and F8MUX. Each has versions with a general output, local
output, or both.
I0
0
LO
I1
1
O
S
DS312-2_35_021205
Figure 18: F5MUX with Local and General Outputs
Table 9: F5MUX Inputs and Outputs
Signal
Function
I0
Input selected when S is Low
I1
Input selected when S is High
S
Select input
LO
Local Output that connects to the F5 or FX CLB
pins, which use local feedback to the FXIN
inputs to the FiMUX for cascading
O
General Output that connects to the
general-purpose combinatorial or registered
outputs of the CLB
Table 10: F5MUX Function
Inputs
S
I0
I1
0
1
X
0
0
X
1
X
1
1
X
0
Outputs
O
LO
1
1
0
0
1
1
0
0
For more details on using the multiplexers, see XAPP466:
"Using Dedicated Multiplexers in Spartan-3 FPGAs".
Carry and Arithmetic Logic
The carry chain, together with various dedicated arithmetic
logic gates, support fast and efficient implementations of
math operations. The carry logic is automatically used for
most arithmetic functions in a design. The gates and multi-
plexers of the carry and arithmetic logic can also be used for
general-purpose logic, including simple wide Boolean func-
tions.
The carry chain enters the slice as CIN and exits as COUT,
controlled by several multiplexers. The carry chain connects
directly from one CLB to the CLB above. The carry chain
can be initialized at any point from the BX (or BY) inputs.
The dedicated arithmetic logic includes the exclusive-OR
gates XORF and XORG (upper and lower portions of the
slice, respectively) as well as the AND gates GAND and
FAND (upper and lower portions, respectively). These gates
work in conjunction with the LUTs to implement efficient
arithmetic functions, including counters and multipliers, typ-
ically at two bits per slice. See Figure 19 and Table 11.
20
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DS312-2 (v1.1) March 21, 2005
Advance Product Specification