XC3S100E Datasheet, PDF (174/193 Pages) Xilinx, Inc – DC and Switching Characteristics

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Pinout Descriptions
FG400: 400-ball Fine-pitch Ball Grid Array
The 400-ball fine-pitch ball grid array, FG400, supports two
different Spartan-3E FPGAs, including the XC3S1200E and
the XC3S1600E. Both devices share a common footprint for
this package as shown in Table 29 and Figure 9.
Table 29 lists all the FG400 package pins. They are sorted
by bank number and then by pin name. Pairs of pins that
form a differential I/O pair appear together in the table. The
table also shows the pin number for each pin and the pin
type, as defined earlier.
An electronic version of this package pinout table and foot-
print diagram is available for download from the Xilinx web-
site at http://www.xilinx.com/bvdocs/publications/s3e_pin.zip.
Pinout Table
Table 29: FG400 Package Pinout
Bank
XC3S1200E
XC3S1600E
Pin Name
0
IO_L09P_0
0
IO_L10N_0
0
IO_L10P_0
0
IO_L11N_0
0
IO_L11P_0
0
IO_L12N_0
0
IO_L12P_0
Table 29: FG400 Package Pinout
Bank
XC3S1200E
XC3S1600E
Pin Name
0
IO
0
IO
0
IO
0
IO
0
IO
0
IO
0
IO
0
IO
0
IO
0
IO
0
IO
0
IO/VREF_0
0
IO_L01N_0
0
IO_L01P_0
0
IO_L03N_0/VREF_0
0
IO_L03P_0
0
IO_L04N_0
0
IO_L04P_0
0
IO_L06N_0
0
IO_L06P_0
0
IO_L07N_0
0
IO_L07P_0
0
IO_L09N_0/VREF_0
FG400
Ball
A3
A8
A12
C7
C10
E8
E13
E16
F13
F14
G7
C11
B17
C17
A18
A19
A17
A16
A15
B15
C14
D14
A13
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VREF
I/O
I/O
VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VREF
0
IO_L14N_0/GCLK5
0
IO_L14P_0/GCLK4
0
IO_L15N_0/GCLK7
0
IO_L15P_0/GCLK6
0
IO_L17N_0/GCLK11
0
IO_L17P_0/GCLK10
0
IO_L18N_0
0
IO_L18P_0
0
IO_L20N_0
0
IO_L20P_0
0
IO_L21N_0/VREF_0
0
IO_L21P_0
0
IO_L23N_0/VREF_0
0
IO_L23P_0
0
IO_L24N_0
0
IO_L24P_0
0
IO_L26N_0
0
IO_L26P_0
0
IO_L27N_0
0
IO_L27P_0
0
IO_L29N_0/VREF_0
0
IO_L29P_0
0
IO_L30N_0
0
IO_L30P_0
0
IO_L31N_0/HSWAP
0
IO_L31P_0
FG400
Ball
A14
B13
C13
C12
D12
E12
F12
G11
F11
E10
E11
A9
A10
F9
E9
C9
D9
B8
B9
F7
F8
A6
A7
B5
B6
D6
C6
C5
D5
A2
B2
D4
C4
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
I/O
I/O
I/O
I/O
VREF
I/O
VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VREF
I/O
I/O
I/O
DUAL
I/O
DS312-4 (v1.1) March 21, 2005
www.xilinx.com
53
Advance Product Specification