XC3S100E Datasheet, PDF (141/193 Pages) Xilinx, Inc – DC and Switching Characteristics

Pinout Descriptions
R
TQ144 Footprint
Note pin 1 indicator in top-left corner and logo orientation.
Double arrows ( ) indicates a pinout migration difference
between the XC3S100E and XC3S250E. Engineering sam-
ple footprint is slightly different.
PROG_B 1
IO_L01P_3 2
IO_L01N_3 3
IO_L02P_3 4
IO_L02N_3/VREF_3 5
IP 6
IO_L03P_3 7
IO_L03N_3 8
VCCINT 9
( ) IP 10
GND 11
IP/VREF_3 12
VCCO_3 13
IO_L04P_3/LHCLK0 14
IO_L04N_3/LHCLK1 15
IO_L05P_3/LHCLK2 16
IO_L05N_3/LHCLK3 17
IP 18
GND 19
IO_L06P_3/LHCLK4 20
IO_L06N_3/LHCLK5 21
IO_L07P_3/LHCLK6 22
IO_L07N_3/LHCLK7 23
IP 24
IO_L08P_3 25
IO_L08N_3 26
GND 27
VCCO_3 28
( ) IP 29
VCCAUX 30
( ) IO/VREF_3 31
IO_L09P_3 32
IO_L09N_3 33
IO_L10P_3 34
IO_L10N_3 35
IP 36
Bank 0
Bank 2
108 TMS
107 IP
106 IO_L10N_1/LDC2
105 IO_L10P_1/LDC1
104 IO_L09N_1/LDC0
103 IO_L09P_1/HDC
102 VCCAUX
101 IP
100 VCCO_1
99 GND
98 IO/A0
97 IO_L08N_1/A1
96 IO_L08P_1/A2
95 IP/VREF_1
94 IO_L07N_1/A3/RHCLK7
93 IO_L07P_1/A4/RHCLK6
92 IO_L06N_1/A5/RHCLK5
91 IO_L06P_1/A6/RHCLK4
90 GND
89 IP
88 IO_L05N_1/A7/RHCLK3
87 IO_L05P_1/A8/RHCLK2
86 IO_L04N_1/A9/RHCLK1
85 IO_L04P_1/A10/RHCLK0
84 IP
83 IO/VREF_1
82 IO_L03N_1/A11
81 IO_L03P_1/A12
80 VCCINT
79 VCCO_1
78 IP
77 IO_L02N_1/A13
76 IO_L02P_1/A14
75 IO_L01N_1/A15
74 IO_L01P_1/A16
73 _GND
Figure 4: TQ144 Package Production Footprint (top view)
DS312-4_01_030705
20
I/O: Unrestricted,
general-purpose user I/O
21
INPUT: Unrestricted,
general-purpose input pin
2
CONFIG: Dedicated
configuration pins
0 ^{N.C.: Not connected}
42
DUAL: Configuration pin, then
possible user I/O
9
VREF: User I/O or input
voltage reference for bank
16
GCLK: User I/O, input, or
global buffer input
9
VCCO: Output voltage supply
for bank
4
JTAG: Dedicated JTAG port
pins
4
VCCINT: Internal core supply
voltage (+1.2V)
13 ^{GND: Ground}
4
VCCAUX: Auxiliary supply
voltage (+2.5V)
20
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DS312-4 (v1.1) March 21, 2005
Advance Product Specification