XC3S100E Datasheet, PDF (81/193 Pages) Xilinx, Inc – DC and Switching Characteristics

Functional Description
R
Table 51: Byte-Wide Peripheral Interface (BPI) Connections (Continued)
Pin Name FPGA Direction
Description
During Configuration
After Configuration
A[23:0]
Output
Address
Connect to PROM address
inputs. High order address lines
may not be available in all
packages and not all may be
required. Number of address
lines required depends on the
size of the attached Flash PROM.
FPGA address generation
controlled by M0 mode pin.
Addresses presented on falling
CCLK edge.
Only 20 address lines are
available in TQ144 package.
User I/O
D[7:0]
Input
Data Input
FPGA receives byte-wide data on
these pins in response the
address presented on A[23:0].
Data captured by FPGA
User I/O If bitstream
option Persist=Yes,
becomes part of
SelectMap parallel
peripheral interface.
CSO_B
Output
Chip Select Output. Active Low.
Not used in single FPGA
applications. In a daisy-chain
configuration, this pin connects to
the CSI_B pin of the next FPGA in
the chain. Actively drives.
User I/O
BUSY
Output
Busy Indicator. Typically only
used after configuration, if
bitstream option Persist=Yes.
Not used during configuration but
actively drives.
User I/O. If bitstream
option Persist=Yes,
becomes part of
SelectMap parallel
peripheral interface.
CCLK
Output
Configuration Clock. Generated
by FPGA internal oscillator.
Frequency controlled by
ConfigRate bitstream generator
option. If CCLK PCB trace is long
or has multiple connections,
terminate this output to maintain
signal integrity.
Not used in single FPGA
applications but actively drives. In
a daisy-chain configuration,
drives the CCLK inputs of all other
FPGAs in the daisy-chain.
User I/O If bitstream
option Persist=Yes,
becomes part of
SelectMap parallel
peripheral interface.
INIT_B
Open-drain
bidirectional I/O
Initialization Indicator. Active
Low. Goes Low at start of
configuration during Initialization
memory clearing process.
Released at end of memory
clearing, when mode select pins
are sampled. In daisy-chain
applications, this signal requires
an external 4.7 kΩ pull-up resistor
to VCCO_2.
Active during configuration. If
CRC error detected during
configuration, FPGA drives
INIT_B Low.
User I/O
74
www.xilinx.com
DS312-2 (v1.1) March 21, 2005
Advance Product Specification