XC3S100E Datasheet, PDF (84/193 Pages) Xilinx, Inc – DC and Switching Characteristics

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Functional Description
Table 54: FPGA Connections to Flash PROM with "IO15/A-1" Pin
Connection to Flash PROM with x8 Flash PROM Interface After x16 Flash PROM Interface After
FPGA Pin
IO15/A-1 Pin
FPGA Configuration
FPGA Configuration
LDC2
BYTE#
Drive LDC2 Low or leave
unconnected and tie PROM
BYTE# input to GND
Drive LCD2 High
LDC1
OE#
Active-Low Flash PROM
output-enable control
Active-Low Flash PROM
output-enable control
LDC0
CS#
Active-Low Flash PROM
chip-select control
Active-Low Flash PROM
chip-select control
HDC
WE#
Flash PROM write-enable
control
Flash PROM write-enable control
A[23:1] A[n:0]
A[n:0]
A[n:0]
A0
IO15/A-1
IO15/A-1 is least-significant
address input
IO15/A-1 is most-significant data
line, IO15
D[7:0]
IO[7:0]
IO[7:0]
IO[7:0]
User I/O
Upper data lines IO[14:8] not
required unless used as x16 Flash
interface after configuration
Upper data lines IO[14:8] not
required
IO[14:8]
Daisy-Chaining
If the application requires multiple FPGAs with different con-
figurations, then configure the FPGAs using a daisy chain,
as shown in Figure 56. Use BPI mode (M[2:0] = <0:1:0> or
<0:1:1>) for the FPGA connected to the parallel NOR Flash
PROM and Slave Parallel mode (M[2:0] = <1:1:0>) for all
other FPGAs in the daisy-chain. After the master
FPGA—the FPGA on the left in the diagram—finishes load-
ing its configuration data from the parallel Flash PROM, the
master device continues generating addresses to the Flash
PROM and asserts its CSO_B output Low, enabling the
next FPGA in the daisy-chain. The next FPGA then receives
parallel configuration data from the Flash PROM. The mas-
ter FPGA’s CCLK output synchronizes data capture.
The downstream devices in Slave Parallel mode also
actively drive their LDC[2:0] and HDC outputs during config-
uration, although these signal are not used for configura-
tion. These pins are in I/O Bank 1, powered by VCCO_1.
Because these pins do not connect elsewhere in the config-
uration circuit, the voltage on VCCO_1 can be whatever is
required by the end application.
DS312-2 (v1.1) March 21, 2005
www.xilinx.com
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