XC3S100E Datasheet, PDF (132/193 Pages) Xilinx, Inc – DC and Switching Characteristics

R
Pinout Descriptions
Table 10: CP132 Package Pinout
Bank
XC3S250E
XC3S500E
Pin Name
2
IO/M1
2
IO/VREF_2
2
IO_L01N_2/INIT_B
2
IO_L01P_2/CSO_B
2
IO_L02N_2/MOSI/CSI_B
2
IO_L02P_2/DOUT/BUSY
2
IO_L03N_2/D6/GCLK13
2
IO_L03P_2/D7/GCLK12
2
IO_L04N_2/D3/GCLK15
2
IO_L04P_2/D4/GCLK14
2
IO_L06N_2/D1/GCLK3
2
IO_L06P_2/D2/GCLK2
2
IO_L07N_2/DIN/D0
2
IO_L07P_2/M0
2
IO_L08N_2/A22
2
IO_L08P_2/A23
2
IO_L09N_2/A20
2
IO_L09P_2/A21
2
IO_L10N_2/VS1/A18
2
IO_L10P_2/VS2/A19
2
IO_L11N_2/CCLK
2
IO_L11P_2/VS0/A17
2
IP/VREF_2
2
IP_L05N_2/M2/GCLK1
2
IP_L05P_2/RDWR_B/
GCLK0
2
VCCO_2
2
VCCO_2
3
IO
3
IO/VREF_3
3
IO_L01N_3
CP132
Ball
N7
P11
N1
M2
N2
P1
N4
M4
N5
M5
P7
P6
N8
P8
M9
N9
M10
N10
M11
N11
N12
P12
N3
N6
M6
M8
P3
J3
K3
B1
Type
DUAL
VREF
DUAL
DUAL
DUAL
DUAL
DUAL/
GCLK
DUAL/
GCLK
DUAL/
GCLK
DUAL/
GCLK
DUAL/
GCLK
DUAL/
GCLK
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
VREF
DUAL/
GCLK
DUAL/
GCLK
VCCO
VCCO
I/O
VREF
I/O
Table 10: CP132 Package Pinout
Bank
XC3S250E
XC3S500E
Pin Name
3
IO_L01P_3
3
IO_L02N_3
3
IO_L02P_3
3
IO_L03N_3
3
IO_L03P_3
3
IO_L04N_3/LHCLK1
3
IO_L04P_3/LHCLK0
3
IO_L05N_3/LHCLK3/IRDY2
3
IO_L05P_3/LHCLK2
3
IO_L06N_3/LHCLK5
3
IO_L06P_3/LHCLK4/TRDY2
3
IO_L07N_3/LHCLK7
3
IO_L07P_3/LHCLK6
3
IO_L08N_3
3
IO_L08P_3
3
IO_L09N_3
3
IO_L09P_3
3
IP/VREF_3
3
VCCO_3
3
VCCO_3
GND GND
GND GND
GND GND
GND GND
GND GND
GND GND
GND GND
GND GND
GND GND
GND GND
GND GND
GND GND
GND GND
GND GND
CP132
Ball
B2
C2
C3
D1
D2
F2
F3
G1
F1
H1
G3
H3
H2
L2
L1
M1
L3
E2
E1
J2
A4
A8
C1
C7
C10
E3
E14
G2
H14
J1
K12
M3
M7
P5
Type
I/O
I/O
I/O
I/O
I/O
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
LHCLK
I/O
I/O
I/O
I/O
VREF
VCCO
VCCO
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
DS312-4 (v1.1) March 21, 2005
www.xilinx.com
11
Advance Product Specification