XC3S100E Datasheet, PDF (91/193 Pages) Xilinx, Inc – DC and Switching Characteristics

Functional Description
R
Intelligent V
Download Host
Configuration
Memory
Source
• Internal memory
• Disk drive
• Over network
• Over RF link
VCC
CLOCK
SERIAL_OUT
PROG_B
DONE
INIT_B
GND
• Microcontroller
• Processor
• Tester
• Computer
+1.2V
P
Slave
Serial
Mode
‘1’
‘1’
‘1’
VCCINT
HSWAP
VCCO_0
VCCO_2
M2
M1
M0
Spartan-3E
CCLK _FPGA
DIN
DOUT
INIT_B
TDI
TMS
TCK
VCCAUX
TDO
PROG_B
GND
DONE
VCCO_0
V
V
+2.5V
+2.5V
PROG_B
Recommend
open-drain
driver
+2.5V
JTAG
TDI
TMS
TCK
TDO
Figure 60: Slave Serial Configuration
DS312-2_54_022305
The mode select pins, M[2:0], are sampled when the
FPGA’s INIT_B output goes High and must be at defined
logic levels during this time. After configuration, when the
FPGA’s DONE output goes High, the mode pins are avail-
able as full-featured user-I/O pins.
P ^{Similarly, the FPGA’s HSWAP pin must be Low to}
enable pull-up resistors on all user-I/O pins or High to dis-
able the pull-up resistors. The HSWAP control must remain
at a constant logic level throughout FPGA configuration.
After configuration, when the FPGA’s DONE output goes
High, the HSWAP pin is available as full-featured user-I/O
pin and is powered by the VCCO_0 supply.
84
www.xilinx.com
DS312-2 (v1.1) March 21, 2005
Advance Product Specification