XC3S100E Datasheet, PDF (59/193 Pages) Xilinx, Inc – DC and Switching Characteristics

Functional Description
R
BUFGMUX Output
X2Y1 (Global)
X0Y2 (Left Half)
Clock Line
A
BUFGMUX Output
X2Y1 (Global)
X3Y2 (Right Half)
Clock Line
A
X2Y0 (Global)
B
X2Y0 (Global)
B
X0Y3 (Left Half)
X3Y3 (Right Half)
X1Y1 (Global)
C
X1Y1 (Global)
C
X0Y4 (Left Half)
X3Y4 (Right Half)
X1Y0 (Global)
D
X1Y0 (Global)
D
X0Y5 (Left Half)
X3Y5 (Right Half)
X2Y11 (Global)
E
X2Y11 (Global)
E
X0Y6 (Left Half)
X3Y6 (Right Half)
X2Y10 (Global)
F
X2Y10 (Global)
F
X0Y7 (Left Half)
X3Y7 (Right Half)
X1Y11 (Global)
G
X1Y11 (Global)
G
X0Y8 (Left Half)
X3Y8 (Right Half)
X1Y10 (Global)
H
X1Y10 (Global)
H
X0Y9 (Left Half)
X3Y9 (Right Half)
a. Left (TL and BL Quadrants) Half of Die
b. Right (TR and BR Quadrants) Half of Die
DS312-2_17_030105
Figure 44: Clock Sources for the Eight Clock Lines within a Clock Quadrant
The outputs of the top or bottom BUFGMUX elements con-
nect to two vertical spines, each comprising four vertical
clock lines as shown in Figure 42. At the center of the die,
these clock signals connect to the eight-line horizontal clock
spine.
Outputs of the left and right BUFGMUX elements are routed
onto the left or right horizontal spines, each comprising
eight horizontal clock lines.
Each of the eight clock signals in a clock quadrant derives
either from a global clock signal or a half clock signal. In
other words, there are up to 24 total potential clock inputs to
the FPGA, eight of which can connect to clocked elements
in a single clock quadrant. Figure 44 shows how the clock
lines in each quadrant are selected from associated BUFG-
MUX sources. For example, if quadrant clock ‘A’ in the bot-
tom left (BL) quadrant originates from BUFGMUX_X2Y1,
then the clock signal from BUFGMUX_X0Y2 is unavailable
in the bottom left quadrant. However, the top left (TL) quad-
rant clock ‘A’ can still solely use the output from either
BUFGMUX_X2Y1 or BUFGMUX_X0Y2 as the source.
To minimize the dynamic power dissipation of the clock net-
work, the Xilinx development software automatically dis-
ables all clock segments not in use.
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DS312-2 (v1.1) March 21, 2005
Advance Product Specification