XC3S100E Datasheet, PDF(116/193 Page) Xilinx, Inc – DC and Switching Characteristics

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

XC3S100E Datasheet, PDF (116/193 Pages) Xilinx, Inc – DC and Switching Characteristics

◁

DC and Switching Characteristics

Configuration and JTAG Timing

VCCINT

1.2V

(Supply)

1.0V

VCCAUX

(Supply)

2.0V

2.5V

VCCO Bank 2

(Supply)

1.0V

PROG_B

(Input)

INIT_B

(Open-Drain)

CCLK

(Output)

TPOR

TPROG

TPL

TICCK

Notes:

DS312-3_01_020505

1. The VCCINT, VCCAUX, and VCCO supplies may be applied in any order.

2. The Low-going pulse on PROG_B is optional after power-on but necessary for reconfiguration without a power cycle.

3. The rising edge of INIT_B samples the voltage levels applied to the mode pins (M0 - M2).

Figure 3: Waveforms for Power-On and the Beginning of Configuration

Table 16: Power-On Timing and the Beginning of Configuration

Symbol

TPOR(2)

TPROG

TPL(2)

TICCK(3)

Description

The time from the application of VCCINT, VCCAUX, and VCCO

Bank 2 supply voltage ramps (whichever occurs last) to the

rising transition of the INIT_B pin

The width of the low-going pulse on the PROG_B pin

The time from the rising edge of the PROG_B pin to the

rising transition on the INIT_B pin

The time from the rising edge of the INIT_B pin to the

generation of the configuration clock signal at the CCLK

output pin

Device

XC3S100E

XC3S250E

XC3S500E

XC3S1200E

XC3S1600E

All

XC3S100E

XC3S250E

XC3S500E

XC3S1200E

XC3S1600E

All

All Speed Grades

Min

Max

0.3

0.5

4.0

Units

Âµs

Notes:

1. The numbers in this table are based on the operating conditions set forth in Table 4. This means power must be applied to all VCCINT, VCCO,

and VCCAUX lines.

2. Power-on reset and the clearing of configuration memory occurs during this period.

3. This specification applies only to the Master Serial, SPI, BPI-Up, and BPI-Down modes.

DS312-3 (v1.0) March 1, 2005

www.xilinx.com

Advance Product Specification

▷