XC3S100E Datasheet, PDF (101/193 Pages) Xilinx, Inc – DC and Switching Characteristics

Functional Description
R
Table 57: Spartan-3E FPGA Bitstream Generator (BitGen) Options (Continued)
Option Name
Pins/Function
Affected
Values
(default)
Description
TdoPin
JTAG TDO pin Pullup Internally connects a pull-up resistor between JTAG TDO pin and VCCAUX.
Pulldown Internally connects a pull-down resistor between JTAG TDO pin and GND.
Pullnone No internal pull-up resistor on JTAG TDO pin.
TmsPin
JTAG TMS pin Pullup Internally connects a pull-up resistor between JTAG TMS pin and VCCAUX.
Pulldown Internally connects a pull-down resistor between JTAG TMS pin and GND.
Pullnone No internal pull-up resistor on JTAG TMS pin.
UserID
JTAG User ID
register
User
string
The 32-bit JTAG User ID register value is loaded during configuration. The default
value is all ones, 0xFFFF_FFFF hexadecimal. To specify another value, enter an
8-character hexadecimal value.
Security
JTAG,
SelectMAP,
Readback,
Partial
reconfiguration
None
Level1
Level
Readback and partial reconfiguration are available via the JTAG port or via the
SelectMAP interface, if the Persist option is set to Yes.
Readback function is disabled. Partial reconfiguration is still available via the JTAG port
or via the SelectMAP interface, if the Persist option is set to Yes.
Readback function is disabled. Partial reconfiguration is disabled.
CRC
Configuration
Enable Default. Enable CRC checking on the FPGA bitstream. If error detected, FPGA
asserts INIT_B Low and DONE pin stays Low.
Disable Turn off CRC checking.
Persist
SelectMAP
interface pins,
BPI mode,
Slave mode,
Configuration
No
All BPI and Slave mode configuration pins are available as user-I/O after configuration.
Yes
This option is required for Readback and partial reconfiguration using the SelectMAP
interface. The SelectMAP interface pins (see Slave Parallel Mode, page 79) are
reserved after configuration and are not available as user-I/O.
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DS312-2 (v1.1) March 21, 2005
Advance Product Specification