XC3S100E Datasheet, PDF (127/193 Pages) Xilinx, Inc – DC and Switching Characteristics

Pinout Descriptions
R
VQ100: 100-lead Very-thin Quad Flat
Package
The XC3S100E and the XC3S250E devices are available in
the 100-lead very-thin quad flat package, VQ100. Both
devices share a common footprint for this package as
shown in Table 7 and Figure 2.
Table 7 lists all the package pins. They are sorted by bank
number and then by pin name of the largest device. Pins
that form a differential I/O pair appear together in the table.
The table also shows the pin number for each pin and the
pin type, as defined earlier.
The VQ100 package does not support the Byte-wide
Peripheral Interface (BPI) configuration mode. Conse-
quently, the VQ100 footprint has fewer DUAL-type pins than
other packages.
An electronic version of this package pinout table and foot-
print diagram is available for download from the Xilinx web
site at http://www.xilinx.com/bvdocs/publications/s3e_pin.zip.
Pinout Table
Table 7 shows the pinout for production Spartan-3E FPGAs
in the VQ100 package. The XC3S100 engineering samples
have a slightly different pinout, as described in Table 9.
Table 7: VQ100 Package Pinout
Bank
XC3S100E
XC3S250E
Pin Name
VQ100
Pin
Number
0 IO
P92
0 IO_L01N_0
P79
0 IO_L01P_0
P78
0 IO_L02N_0/GCLK5
P84
0 IO_L02P_0/GCLK4
P83
0 IO_L03N_0/GCLK7
P86
0 IO_L03P_0/GCLK6
P85
0 IO_L05N_0/GCLK11
P91
0 IO_L05P_0/GCLK10
P90
0 IO_L06N_0/VREF_0
P95
0 IO_L06P_0
P94
0 IO_L07N_0/HSWAP
P99
0 IO_L07P_0
P98
0 IP_L04N_0/GCLK9
P89
0 IP_L04P_0/GCLK8
P88
0 VCCO_0
P82
Type
I/O
I/O
I/O
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
VREF
I/O
DUAL
I/O
GCLK
GCLK
VCCO
Table 7: VQ100 Package Pinout
Bank
XC3S100E
XC3S250E
Pin Name
VQ100
Pin
Number
Type
0 VCCO_0
P97
VCCO
1 IO_L01N_1
P54
I/O
1 IO_L01P_1
P53
I/O
1 IO_L02N_1
P58
I/O
1 IO_L02P_1
P57
I/O
1 IO_L03N_1/RHCLK1
P61
RHCLK
1 IO_L03P_1/RHCLK0
P60
RHCLK
1 IO_L04N_1/RHCLK3
P63
RHCLK
1 IO_L04P_1/RHCLK2
P62
RHCLK
1 IO_L05N_1/RHCLK5
P66
RHCLK
1 IO_L05P_1/RHCLK4
P65
RHCLK
1 IO_L06N_1/RHCLK7
P68
RHCLK
1 IO_L06P_1/RHCLK6
P67
RHCLK
1 IO_L07N_1
P71
I/O
1 IO_L07P_1
P70
I/O
1 IP/VREF_1
P69
VREF
1 VCCO_1
P55
VCCO
1 VCCO_1
P73
VCCO
2 IO/D5
P34
DUAL
2 IO/M1
P42
DUAL
2 IO_L01N_2/INIT_B
P25
DUAL
2 IO_L01P_2/CSO_B
P24
DUAL
2 IO_L02N_2/MOSI/CSI_B
P27
DUAL
2
IO_L02P_2/DOUT/BUSY
P26
DUAL
2 IO_L03N_2/D6/GCLK13
P33 DUAL/GCLK
2 IO_L03P_2/D7/GCLK12
P32 DUAL/GCLK
2 IO_L04N_2/D3/GCLK15
P36 DUAL/GCLK
2 IO_L04P_2/D4/GCLK14
P35 DUAL/GCLK
2 IO_L06N_2/D1/GCLK3
P41 DUAL/GCLK
2 IO_L06P_2/D2/GCLK2
P40 DUAL/GCLK
2 IO_L07N_2/DIN/D0
P44
DUAL
2 IO_L07P_2/M0
P43
DUAL
2 IO_L08N_2/VS1
P48
DUAL
2 IO_L08P_2/VS2
P47
DUAL
6
www.xilinx.com
DS312-4 (v1.1) March 21, 2005
Advance Product Specification