XC3S100E Datasheet, PDF (181/193 Pages) Xilinx, Inc – DC and Switching Characteristics

Pinout Descriptions
FG400 Footprint
Left Half of Package
(top view)
156
I/O: Unrestricted,
general-purpose user I/O
INPUT: User I/O or
62 reference resistor input for
bank
46
DUAL: Configuration pin,
then possible user I/O
24
VREF: User I/O or input
voltage reference for bank
16
GCLK: User I/O, input, or
clock buffer input
2
CONFIG: Dedicated
configuration pins
4
JTAG: Dedicated JTAG
port pins
42 ^{GND: Ground}
24
VCCO: Output voltage
supply for bank
16
VCCINT: Internal core
supply voltage (+1.2V)
8
VCCAUX: Auxiliary supply
voltage (+2.5V)
0 ^{N.C.: Not connected}
R
Bank 0
1
2
3
4
5
6
7
8
9
10
A GND
I/O
L30N_0
I/O
INPUT INPUT I/O
I/O
L28N_0 L28P_0 L24N_0 L24P_0
I/O
I/O
L17N_0
GCLK11
I/O
L17P_0
GCLK10
B
I/O
L03P_3
I/O
L30P_0
TDI
VCCO_0
I/O
I/O
L26N_0 L26P_0
GND
I/O
L21N_0
VREF_0
I/O
L21P_0
VCCO_0
C
I/O
L03N_3
PROG_B
GND
I/O
L31P_0
I/O
L29N_0
VREF_0
I/O
L27P_0
I/O
INPUT I/O
L22N_0 L20N_0
I/O
D
I/O
L04P_3
I/O
L01N_3
I/O
L01P_3
I/O
L31N_0
HSWAP
I/O
L29P_0
I/O
VCCO_0 ^INPUT
L27N_0
L22P_0
I/O
L20P_0
GND
E
I/O
L04N_3
VCCO_3
I/O
L02N_3
VREF_3
I/O
L02P_3
INPUT
INPUT
L25N_0
INPUT
L25P_0
I/O
I/O
L18P_0
I/O
L15N_0
GCLK7
F
I/O
L06N_3
I/O
L06P_3
I/O
L05N_3
I/O
L05P_3
INPUT
GND
I/O
L23N_0
VREF_0
I/O
L23P_0
I/O
VCCO_0
L18N_0
G INPUT
GND
I/O
I/O
I/O
INPUT
L07P_3 L07N_3 L08N_3
I/O
INPUT
L19P_0
INPUT
L19N_0
INPUT
L16N_0
GCLK9
H INPUT
I/O
L09P_3
I/O
L09N_3
VREF_3
VCCO_3
I/O
L08P_3
I/O
L10P_3
I/O
L10N_3
GND
INPUT
VCCINT L16P_0
GCLK8
J
I/O
L12N_3
I/O
L12P_3
I/O
L11P_3
I/O
L11N_3
INPUT
I/O
VCCAUX VCCINT
L13N_3
GND
VCCINT
K GND
I/O
L L16N_3
LHCLK5
I/O
M
L16P_3
LHCLK4
TRDY2
N
I/O
L21P_3
P
I/O
L24P_3
R
I/O
L24N_3
I/O
T L28N_3
VREF_3
U
I/O
L28P_3
V
I/O
L30N_3
W INPUT
I/O
L14N_3
LHCLK1
VCCO_3
INPUT
I/O
L21N_3
GND
I/O
L26P_3
I/O
L26N_3
VCCO_3
I/O
L30P_3
INPUT
L02P_2
I/O
L14P_3
LHCLK0
I/O
L17N_3
LHCLK7
I/O
L17P_3
LHCLK6
I/O
L23P_3
INPUT
I/O
L27P_3
I/O
L29N_3
I/O
L29P_3
GND
INPUT
VCCAUX
GND
I/O
L19N_3
I/O
L23N_3
VCCO_3
I/O
L27N_3
INPUT
I/O
L01P_2
CSO_B
I/O
L01N_2
INIT_B
I/O
L04P_2
INPUT
VREF_3
INPUT
I/O
L19P_3
INPUT
I/O
L25P_3
I/O
L25N_3
I/O
L06P_2
I/O
L03P_2
DOUT
BUSY
I/O
L03N_2
MOSI
CSI_B
VCCO_2
I/O
L13P_3
VCCO_3
I/O
L20P_3
I/O
L20N_3
VREF_3
INPUT
VREF_3
GND
I/O
L06N_2
INPUT
L05P_2
INPUT
L05N_2
INPUT
L08P_2
I/O
L15P_3
LHCLK2
I/O
L15N_3
LHCLK3
IRDY2
GND VCCINT GND
INPUT GND VCCINT
I/O
I/O _{VCCINT GND}
L18N_3 L18P_3
I/O _{VCCINT VCCAUX VCCINT}
L22P_3
I/O
L22N_3
I/O
L09N_2
VREF_2
I/O
L09P_2
I/O
INPUT
L11N_2
INPUT
L11P_2
GND
I/O
INPUT
L14P_2
I/O
L16N_2
D3
GCLK15
I/O
L16P_2
D4
GCLK14
INPUT
L14N_2
VREF_2
I/O
VCCO_2
I/O
VCCAUX
L07N_2
L12N_2
I/O
L07P_2
GND
I/O
L10N_2
I/O
L10P_2
I/O
L12P_2
I/O
L15P_2
D7
GCLK12
I/O
L18P_2
D2
GCLK2
I/O
L15N_2
D6
GCLK13
Y GND
INPUT I/O
I/O
L02N_2 VREF_2 L04N_2
I/O
INPUT
L08N_2
I/O
I/O
I/O
L13N_2 L13P_2
GND
Bank 2
Figure 9: FG400 Package Footprint (top view)
DS312-4_08_031105
60
www.xilinx.com
DS312-4 (v1.1) March 21, 2005
Advance Product Specification